Modelsim and Warning: NUMERIC_STD.TO_INTEGER: metavalue dete

[Olaf]

Hi,

during my simulation I get the warning above. Anyway I know what it
means and that is a result of an initializing problem on simulation (and
even using std_logic ...). To be concrete it occours at t = 0 and t =
Clk/2. The 2nd warning I get rip up by initialitzing some internal
architectures signals to '0'.

Anyway, is there a way to ommit this warnigns at special times, e.g. for
t=0 ?? It may confuse me on 'bug hunting' ;-)

Thanks,
Olaf

 

[Tricky]

On 5 Dec, 10:41, Olaf <is...@inter.net> wrote:

Hi,

during my simulation I get the warning above. Anyway I know what it
means and that is a result of an initializing problem on simulation (and
even using std_logic ...). To be concrete it occours at t = 0 and t =
Clk/2. The 2nd warning I get rip up by initialitzing some internal
architectures signals to '0'.

Anyway, is there a way to ommit this warnigns at special times, e.g. for
t=0 ?? It may confuse me on 'bug hunting' ;-)

Thanks,
Olaf

You cannot suppress warnings at given times.

There are 2 options for you:
1. Give the unsigned/signed value(s) that are giving the problem
initial values
2. in modelsim go to Simulate -> Runtime Options -> Suppress warnings
from IEEE numeric Std Packages. This also blocks the warnings if
you're converting an integer that's too big for the array (which is
then truncated). It wont supress warnings from when you try and
convert a -ve integer into an unsigned though.

 

[Jonathan Bromley]

On Fri, 5 Dec 2008 03:08:31 -0800 (PST), Tricky wrote:

warnings at given times.

True, but you can get the same effect using a simple run
script - so simple that you could easily type it at the
command line:

set NumericStdNoWarnings 1
run 20 ns ;# or whatever you need to get past the problem
set NumericStdNoWarnings 0
run -all ;# warnings enabled for the remainder of the run

A note for the Tcl-savvy: Variable ::NumericStdNoWarnings
does not exist by default. Instead, the control of that
behaviour is determined from the modelsim.ini file. But
if the variable *does* exist, because you created it, then
its value is used to control the behaviour and overrides
the setting from modelsim.ini.

Take care to get the variable name just right.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

Olaf wrote:

during my simulation I get the warning above. Anyway I know what it
means and that is a result of an initializing problem on simulation (and
even using std_logic ...). To be concrete it occours at t = 0 and t =
Clk/2. The 2nd warning I get rip up by initialitzing some internal
architectures signals to '0'.

I give *all* of my *testbench* signals simple initial values.
This seems to solve the problem for my design style.

-- Mike Treseler

 

[Jim Lewis]

Olaf

Anyway, is there a way to ommit this warnigns at special times, e.g. for
t=0 ?? It may confuse me on 'bug hunting' ;-)
I print out a marker message that indicates when a design comes

out of reset. Alternately see Jonathan's post if you
are using modelsim.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis SynthWorks VHDL Training http://www.synthworks.com

A bird in the hand may be worth two in the bush,
but it sure makes it hard to type.