Modelsim and negative timing checks

[Paul Richardson]

I seem to be having problems with negative timing checks in Modelsim: Išll
try and describe what I see to be the problem below:

I have a flip-flop model and it is back annotated with the following sdf
information:
(SETUPHOLD (posedge D) (posedge CK) (0.141667:0.141667:0.141667)
(-0.141667:-0.141667:-0.141667))
(SETUPHOLD (negedge D) (posedge CK) (0.154051:0.154051:0.154051)
(-0.154051:-0.154051:-0.154051)).
(IOPATH (posedge CK) Q (0.228859:0.228859:0.228859)
(0.237833:0.237833:0.237833))

From the information above, I would expect that a low-to-high transition on
the D input of this flop occurring 141 ps or more before the rising edge of
the clock would meet meet the setup time. Hold time, because of its negative
value (magnitude equal to setup) is not an issue. The Q output would
transition 228 ps later

In the case of a high-to-low transition on the D input, the requirement is
that it occur 154 ps before the rising edge of the clock in order to meet
timing, the reasoning for the negative hold time remains the same, and the
output Q transitions 237 ps after the rising edge of the clock.

In my simulations I observe the D input transitioning low-high 3ps before
the rising edge of the clock and the output transitioning 228 ps later. I
would expect that since I have violated the setup time, I would get a timing
error indicating the violation and (because of the way we have the flip flop
modeled) see an X on the output of the flop.

Am I missing something, timing checks and specify blocks are enabled, I have
left modelsim in its default mode of inertial delays. And even tried fooling
around with the extend_tcheck_data_limit switch...

 

[Navneet Rao]

Unless ofcourse... you have an excellent library..which has timescales
in "fs"
and your simulation uses "ps"

Paul Richardson wrote:

I seem to be having problems with negative timing checks in Modelsim:
I’ll try and describe what I see to be the problem below:

I have a flip-flop model and it is back annotated with the following
sdf information:
(SETUPHOLD (posedge D) (posedge CK)
(0.141667:0.141667:0.141667) (-0.141667:-0.141667:-0.141667))
(SETUPHOLD (negedge D) (posedge CK)
(0.154051:0.154051:0.154051) (-0.154051:-0.154051:-0.154051)).
(IOPATH (posedge CK) Q (0.228859:0.228859:0.228859)
(0.237833:0.237833:0.237833))

From the information above, I would expect that a low-to-high
transition on the D input of this flop occurring 141 ps or more before
the rising edge of the clock would meet meet the setup time. Hold
time, because of its negative value (magnitude equal to setup) is not
an issue. The Q output would transition 228 ps later

In the case of a high-to-low transition on the D input, the
requirement is that it occur 154 ps before the rising edge of the
clock in order to meet timing, the reasoning for the negative hold
time remains the same, and the output Q transitions 237 ps after the
rising edge of the clock.

In my simulations I observe the D input transitioning low-high 3ps
before the rising edge of the clock and the output transitioning 228
ps later. I would expect that since I have violated the setup time, I
would get a timing error indicating the violation and (because of the
way we have the flip flop modeled) see an X on the output of the flop.

Am I missing something, timing checks and specify blocks are enabled,
I have left modelsim in its default mode of inertial delays. And even
tried fooling around with the extend_tcheck_data_limit switch...