ModelSim / Altera Error

[Rob]

Hello,

Does anyone know what this error means? It seems as if the tool is
reporting a hold violation but I'm not sure how to locate it because
it isn't telling me what atom.

Error: C:/ModelSim_Altera72/modelsim_ae/win32aloem/../altera/verilog/
src/cycloneiii_atoms.v(4175): $hold( posedge clk &&& reset:2268 ps, d:
2345 ps, 254 ps );

Thank you,
Rob

 

[Jonathan Bromley]

On Thu, 18 Dec 2008 09:17:55 -0800 (PST), Rob
<robnstef@frontiernet.net> wrote:

Hello,

Does anyone know what this error means? It seems as if the tool is
reporting a hold violation but I'm not sure how to locate it because
it isn't telling me what atom.

Error: C:/ModelSim_Altera72/modelsim_ae/win32aloem/../altera/verilog/
src/cycloneiii_atoms.v(4175): $hold( posedge clk &&& reset:2268 ps, d:
2345 ps, 254 ps );

Did you look at the NEXT line of output message? Normally that
will show you various other pieces of information including the
simulation time when the hold violation occurred, and the
Verilog path to the module in which it happened.

If not, then you can change it. Find out where ModelSim's
working directory is (you can ask: type the command "pwd"
at the ModelSim command line) and in that directory take a
look at the modelsim.ini file. In it you should find
something looking a bit like this:

; VHDL assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %i - Instance pathname with process
[and much more]
; MessageFormatError = "** %S: %R\n Time: %T
Iteration: %D %K: %i File: %F\n"

Yes, I know it says VHDL, but these message templates work for
Verilog as well. Remove the semicolon comment character from
the MessageFormatError line, and make sure that the %i or %I
placeholder appears somewhere in the string. This will give
you the path to your offending module.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[gabor]

On Dec 18, 12:17 pm, Rob <robns...@frontiernet.net> wrote:

Hello,

Does anyone know what this error means?  It seems as if the tool is
reporting a hold violation but I'm not sure how to locate it because
it isn't telling me what atom.

Error: C:/ModelSim_Altera72/modelsim_ae/win32aloem/../altera/verilog/
src/cycloneiii_atoms.v(4175): $hold( posedge clk &&& reset:2268 ps, d:
2345 ps, 254 ps );

Thank you,
Rob

You have a file name .../cycloneiii_atoms.v
and a line number 4175

Theoretically you can place a breakpoint on that line and see
where you are in the hierarchy when the breakpoint trips.

 

[Rob]

Jonathan,

Thank you.

Rob

Jonathan Bromley wrote:

On Thu, 18 Dec 2008 09:17:55 -0800 (PST), Rob
robnstef@frontiernet.net> wrote:

Hello,

Does anyone know what this error means? It seems as if the tool is
reporting a hold violation but I'm not sure how to locate it because
it isn't telling me what atom.

Error: C:/ModelSim_Altera72/modelsim_ae/win32aloem/../altera/verilog/
src/cycloneiii_atoms.v(4175): $hold( posedge clk &&& reset:2268 ps, d:
2345 ps, 254 ps );

Did you look at the NEXT line of output message? Normally that
will show you various other pieces of information including the
simulation time when the hold violation occurred, and the
Verilog path to the module in which it happened.

If not, then you can change it. Find out where ModelSim's
working directory is (you can ask: type the command "pwd"
at the ModelSim command line) and in that directory take a
look at the modelsim.ini file. In it you should find
something looking a bit like this:

; VHDL assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %i - Instance pathname with process
[and much more]
; MessageFormatError = "** %S: %R\n Time: %T
Iteration: %D %K: %i File: %F\n"

Yes, I know it says VHDL, but these message templates work for
Verilog as well. Remove the semicolon comment character from
the MessageFormatError line, and make sure that the %i or %I
placeholder appears somewhere in the string. This will give
you the path to your offending module.