Modelling log2-quantiser

[Florian Schlembach]

I need some advise modeling a log2-quantiser. Here is my minimal example:

log2(7000) = 12.7731
7000 in binary is: 0011001011001000

It's quite obvious that a log2 of a binary number is the bit-position of the leftmost 1 of the binary number (floor operation).

My question is now how to model this log2-quantiser? Certainly, I can use a for-loop and look for the leftmost 1 but I reckon this is not the right way? How would a for-loop then be synthesised?

So, is there a smart way how to model such a log2-quantiser in order to implement in efficiently into hardware?

 

[Florian Schlembach]

I just discovered the $clog system function. How is this one being synthesised?

 

[Mark Curry]

In article <297b60ba-de57-4330-af36-b45f94e0c709@googlegroups.com>,
Florian Schlembach <florian.schlembach@gmail.com> wrote:

I just discovered the $clog system function. How is this one being
synthesised?

Florian,

Well, it depends. I know that Xilinx FPGA tools do not compile it at all -
you have to roll your own.

Most of us have done so for log2, and yes you use a for loop. For an example
see:
http://www.beyond-circuits.com/wordpress/2008/11/constant-functions/

Now, as to synthesis results (of bare $clog, or a user-written one like above) -
it depends - most of the time it's used on constants. So, it's just
compiler crunching, and a constant pops out.

For log2 of a variable - then yes, it's going to build a (perhaps) inefficient
cone of logic. But it should work fine as long as your bit-widths are reasonable.
You'll start to run into critical paths pretty quick as your bit widths grows,
and you'll need to re-evaluate your needs / architecture...

Regards,

Mark

 

[Kevin Neilson]

The $clog2() function works in Synplify and I use it all the time. However, it's a synthesis-time function and won't create any hardware. It's good for stuff like this:

parameter RAM_DEPTH = 1024;
reg [$clog2(RAM_DEPTH)-1:0] ram_addr;

 

[GaborSzakacs]

Mark Curry wrote:

In article <297b60ba-de57-4330-af36-b45f94e0c709@googlegroups.com>,
Florian Schlembach <florian.schlembach@gmail.com> wrote:
I just discovered the $clog system function. How is this one being
synthesised?

Florian,

Well, it depends. I know that Xilinx FPGA tools do not compile it at all -
you have to roll your own.

Most of us have done so for log2, and yes you use a for loop. For an example
see:
http://www.beyond-circuits.com/wordpress/2008/11/constant-functions/

Now, as to synthesis results (of bare $clog, or a user-written one like above) -
it depends - most of the time it's used on constants. So, it's just
compiler crunching, and a constant pops out.

For log2 of a variable - then yes, it's going to build a (perhaps) inefficient
cone of logic. But it should work fine as long as your bit-widths are reasonable.
You'll start to run into critical paths pretty quick as your bit widths grows,
and you'll need to re-evaluate your needs / architecture...

Regards,

Mark

I recently tried $clog2 in XST 13.4 and found:

1. It actually computes ceiling ln(x) rather than ceiling log2(x)

2. Isim doesn't support it.

There is an Answer record about this with a suggested workaround
function (using a loop), and a statement that the bug would be
fixed in ISE 14.1 (I haven't tried it yet). In the meantime I have
used their workaround which works fine:

function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction


-- Gabor

 

[Chris Briggs]

What about casez? I've seen this structure used for years.

casez (value)
16'b 1???_????_????_????: pos = 15;
16'b 01??_????_????_????: pos = 14;
16'b 001?_????_????_????: pos = 13;
16'b 0001_????_????_????: pos = 12;
16'b 0000_1???_????_????: pos = 11;
etc.
endcase

Simple and synthesizable.

-cb


On Friday, February 22, 2013 12:08:33 PM UTC-5, Florian Schlembach wrote:

I need some advise modeling a log2-quantiser. Here is my minimal example:



log2(7000) = 12.7731

7000 in binary is: 0011001011001000



It's quite obvious that a log2 of a binary number is the bit-position of the leftmost 1 of the binary number (floor operation).



My question is now how to model this log2-quantiser? Certainly, I can use a for-loop and look for the leftmost 1 but I reckon this is not the right way? How would a for-loop then be synthesised?



So, is there a smart way how to model such a log2-quantiser in order to implement in efficiently into hardware?

 

[Kevin Neilson]

Ha ha, that does not surprise me. How hard can this be? It only takes two lines of code and it's been in the spec for eight years. I guess you can put it in a package and use it when you need it, if XST supports Verilog packages.

 

[unfrostedpoptart]

On Monday, February 25, 2013 9:16:05 AM UTC-8, Kevin Neilson wrote:

The $clog2() function works in Synplify and I use it all the time. However, it's a synthesis-time function and won't create any hardware. It's good for stuff like this:

parameter RAM_DEPTH = 1024;
reg [$clog2(RAM_DEPTH)-1:0] ram_addr;

Yes - use this all the time. However, be careful if you use this generically throughout a design and instantiated with various sizes. In the case where an object is only a single bit:

parameter BITS = 1;
logic [BITS-1:0] my_vector;
logic [$clog2(BITS)-1:0] my_vector_index;

In his case, my_vector is [0:0], which is annoying but legal (why can't the 1800 group ever figure out a clean way to handle scalar vs single-bit vector???).

However, $clog2(1) == 0 which gives you my_vector_index[-1:0], which is very bad.
It does make sense since you don't need an index to a single bit. However, it creates headaches with re-usable code.

A simple macro can catch this:

`define MY_CLOG2(a) (a>1)?$clog2(a):1

David