modelling a FIFO in VHDL

[fpgawizz]

I am trying to send data via RS 232 to a spartan 3 development board that
has external SRAM. I want to send data to the RXD input of the FPGA and
have the FPGA send this to the SRAM. This is a simplex transmission from
my PC to the FPGA that is listening. Is there any models I can see or use
maybe for doing this kind of a UART, FIFO in VHDL ?

 

[Jezwold]

I assume that you have heard of the google search engine,well I suggest
you give that a try because i did and it worked for me.