Modeling two dimensional circuits

[vssumesh]

Hello all,
I am now trying to code a bough wooley multiplier in verilog. The
following link gives good animation and VHDL code for that.
http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Multip.htm
Is it possible to get a verilog code as simple as the VHDL code shown
in the site. i tried to model it but have some doubt.

Is it possible to instantiate two dimensional components in verilog.
There is options for 1 dimensional instantiations But when i tried for
two dimension it gave an error. I tried the following syntax..
FA fa[7:0][6:0](in1[7:0][6:0],out[7:0][6:0]); etc....
but FA fa[7:0](in1[7:0],out[7:0]); worked just fine.
Also i felt like books and related topics on this type advanced design
is very less. Requesting evry bodies comment on this.
regards
Sumesh

 

[vssumesh]

I sucess fully created a two dimensional structure for unsigned
multiplier, using multiple "one dimensional instantiations". it
synthesized correctly but simulator gave error values. All code seems
ok i also verified it in the output of the synthesizer but in simulator
its not working.
What is the standard procedure to describe a circuit which is
repeatation of small units(like the multiplier).
I think we can use the "for" loop for that (i used the same in my
design).
But it can be included only in the always blocks ?? is there any other
way for that?
IS there any other way in which we can simply specify the connections
as is done in schematic editor ??
regards sumesh

 

Arrays of instances can only be 1-dimensional in Verilog. You can
always map a multi-dimensional array into a 1-dimensional array anyway.
Alternately, you could instantiate an array of instances, each of
which handles an entire row by instantiating an array of instances to
handle the individual elements.

Verilog-1995 only supported 1-dimensional arrays of data words also.
Multi-dimensional arrays were only added in Verilog-2001.
Multi-dimensional arrays of instances were probably not added because
attention was focused on adding the more general generate constructs to
do the same kind of things, rather than extending arrays of instances.

 

[vssumesh]

Thanks for the suggestion. I am experimenting with the generate key
word.
But while doing that some problem observed. the following code gave
error.
"index out of range".

for(i = 0; i<= 7;i=i+1)
begin
assign A = (i!=0)?B&C[i-1]:1;
end

because of this error i am forced to split the loop. Is there any way
to do this in a single loop???

 

vssumesh wrote:

Thanks for the suggestion. I am experimenting with the generate key
word.
But while doing that some problem observed. the following code gave
error.
"index out of range".

for(i = 0; i<= 7;i=i+1)
begin
assign A = (i!=0)?B&C[i-1]:1;
end

This may only be a warning, since the behavior is perfectly well
defined in Verilog. And since the C[i-1] part is thrown away when i
was zero, it really doesn't matter. However, perhaps your tool is
being extra strict.

because of this error i am forced to split the loop. Is there any way
to do this in a single loop???

Well, you could keep the index in range in the i==0 case also, even
though you are throwing it away, with something like

assign A = (i!=0)?B&C[(i!=0)?(i-1):0]:1;

Or you could put a generate-if inside the generate-for-loop:

for(i=0; i<=7; i=i+1)
begin
if (i!=0)
assign A = B&C[i-1];
else
assign A = 1;
end

BTW, if A, B and C are vectors, then this is a very inefficient way to
do this. Why use 8 continuous assignments of 1 bit at a time, when you
could do a single vector continuous assignment? This code only makes
sense if these are arrays of multi-bit vectors.