Modeling strength to model steady-state analogue signals (cu

[Andy Luotto]

I am thinking to use strength for this, e.g. VDD is a supply1 and VSS
is a supply0. Then I am thinking about currents, e.g. using weak or
medium strengths ina digital simulator.
Still It is not completely clear how to do this: while

supply1 vdd;

compile, I cannot find a way to define a wire of type weak0 or
medium0, e.g.

weak0 idd;

maybe a should define a buffer buf (weak1, weak0) to drive a current
output or someth

the examples in http://www.verilog.renerta.com/source/vrg00047.htm
does not shade any lihght on this

please daviuce

cheers