Modeling pullup on the input

[YK]

Hi

Is there a way to model a pullup on the input of a module without
using any internal signal like the verilog-HDL pullup.

If I model using a pullup map as below:

test_ipd <= pullupmap(TO_X01Z(test))

constant pullupmap : vitalresultzmaptype := ( 'X', 'X', '0', '1',
'H');

I can see that test_ipd is pulled up when test is 'Z'. But is it
possible to model such that pullup can be seen on "test" signal
instead of "test_ipd".

 

[KJ]

"YK" <ykmayee@yahoo.com> wrote in message
news:1185495755.824311.59560@k79g2000hse.googlegroups.com...

Hi

Is there a way to model a pullup on the input of a module without
using any internal signal like the verilog-HDL pullup.
Yes, to model a pullup on signal 'xyz', you simply add the statement 'xyz <=

'H'' to your simulation model.

If I model using a pullup map as below:

test_ipd <= pullupmap(TO_X01Z(test))
Unfortunately this is modelling something else. What you've done is created

two signals 'test' and 'test_ipd' and created a model to separate them. But
that's not the way a pullup works. A pullup does not create a new signal,
it adds a new driver to an existing signal.

constant pullupmap : vitalresultzmaptype := ( 'X', 'X', '0', '1',
'H');

I can see that test_ipd is pulled up when test is 'Z'. But is it
possible to model such that pullup can be seen on "test" signal
instead of "test_ipd".

Below is a template for how you would go about modelling all of this.

entity testbench is
end testbench;
architecture RTL of testbench
signal Some_Input, Some_Output: std_logic
begin

------------------------------------------
-- DUT is the design you're trying to test
-- It has a single input and a single output
------------------------------------------
DUT : entity work.My_Design port map(
gazinta => Some_Input,
gazouta => Some_Output);

------------------------------------------
-- Lets put a pullup on 'Some_Input' and just for grins
-- put a pulldown on 'Some_Output'
------------------------------------------
Some_Input <= 'H';
Some_Output <= 'L';

------------------------------------------
-- Now lets create some arbitrary input stimulus
-- to model whatever it is that the input signal is supposed to do
------------------------------------------
process
begin
for i in 1 to 10 loop
Some_Input <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
Some_Input <= 'Z';
wait; -- Wait forever
end process;

What you'll see on 'Some_Input' is that it toggles about between '1' and '0'
for 50 ns and then goes to 'H' because 'Some_Input' has two drivers; the
line "Some_Input <= 'H';" and the process above. The 'process' ends by
trying to drive the net to 'Z', the resolve function of the VHDL model for
std_logic takes the 'H' and 'Z' and resolves that to be 'H'. Similar things
would be going on with the output (whatever it does) and the 'L'.

If you stand back and take the high level look at the structure of this
testbench you would see your FPGA/CPLD (the 'My_Design' entity), a pullup
and pulldown resistor attached to some signals and then a process that
models whatever the input to 'My_Design' is....you're in fact modelling the
PCBA so you stick the pullup/down as drivers on the signals that model the
nets in your PCBA.

KJ

 

[ast]

"YK" <ykmayee@yahoo.com> a écrit dans le message de news: 1185495755.824311.59560@k79g2000hse.googlegroups.com...

Hi

Is there a way to model a pullup on the input of a module without
using any internal signal like the verilog-HDL pullup.

If I model using a pullup map as below:

test_ipd <= pullupmap(TO_X01Z(test))

constant pullupmap : vitalresultzmaptype := ( 'X', 'X', '0', '1',
'H');

I can see that test_ipd is pulled up when test is 'Z'. But is it
possible to model such that pullup can be seen on "test" signal
instead of "test_ipd".

State H (weak high) of type std_logic

 

[YK]

On Jul 27, 10:15 am, "ast" <a...@ast.com> wrote:

"YK" <ykma...@yahoo.com> a écrit dans le message de news: 1185495755.824311.59...@k79g2000hse.googlegroups.com...





Hi

Is there a way to model a pullup on the input of a module without
using any internal signal like the verilog-HDL pullup.

If I model using a pullup map as below:

test_ipd <= pullupmap(TO_X01Z(test))

constant pullupmap : vitalresultzmaptype := ( 'X', 'X', '0', '1',
'H');

I can see that test_ipd is pulled up when test is 'Z'. But is it
possible to model such that pullup can be seen on "test" signal
instead of "test_ipd".

State H (weak high) of type std_logic- Hide quoted text -

- Show quoted text -

Thanks for your reply. Pardon me if I didn't understand the reply
correctly. Let me explain my problem in detail.

I am trying to write a simulation model for an input buffer with pull
up resistor. I want to model the pullup on the input port of a module,
not on the signal in the module.

The module is written below(didn't include the port delays and path
delays section)

entity inbuf is

port(PAD : in std_logic;
Yut std_logic);

end entity;

architecture buf_arch of inbuf is
pad_ipd : std_logic;
begin

pad_ipd <= 'H';
pad_ipd <= pad;
vitalbehavior : process(pad_ipd)--in this vitalpathdelay section is
not included
variable Y_zd : std_logic;
begin
Y_zd := TO_X01(pad_ipd);
end process

end buf_arch;


Now if the user simulates using this simulation model, he will able to
see the pullup on the pad_ipd signal only, not on the pad signal
directly. Again the pad_ipd is added just for user to be able to see
the pulledup input signal. Is there a way to show the pullup on "pad"
to the user.

If we do this in verilog

module inbuf(pad,y)
input pad;
output y;

pullup upd(pad)
buf buf_inst(y,pad);

endmodule.

As you can see here, when the user simulates with this model he will
be able to see that "pad" is pulled up.

I am trying to get this behavior in vital simulation model.


Thanks

 

[KJ]

"YK" <ykmayee@yahoo.com> wrote in message
news:1185568557.877163.151490@x35g2000prf.googlegroups.com...
On Jul 27, 10:15 am, "ast" <a...@ast.com> wrote:

"YK" <ykma...@yahoo.com> a écrit dans le message de news:
1185495755.824311.59...@k79g2000hse.googlegroups.com...



Hi

Is there a way to model a pullup on the input of a module without
using any internal signal like the verilog-HDL pullup.
Like I said before....just add a driver of 'H' to the signal in question.

Thanks for your reply. Pardon me if I didn't understand the reply
correctly. Let me explain my problem in detail.

I am trying to write a simulation model for an input buffer with pull
up resistor. I want to model the pullup on the input port of a module,
not on the signal in the module.

The module is written below(didn't include the port delays and path
delays section)

Doesn't appear that you understood my post either....What you need is shown
below (marked up from your posting)

entity inbuf is

port(PAD : inout std_logic); -- Yes...it needs to be inout
-- Don't need this... Yut std_logic);

end entity;

architecture buf_arch of inbuf is
--- Don't need this... pad_ipd : std_logic;
begin

pad <= 'H';
---- don't need this pad_ipd <= pad;
-- Don't need this...vitalbehavior : process(pad_ipd)--in this
vitalpathdelay section is
-- Don't need this...not included
-- Don't need this...variable Y_zd : std_logic;
-- Don't need this...begin
-- Don't need this...Y_zd := TO_X01(pad_ipd);
-- Don't need this...end process

end buf_arch;

A pullup represents another DRIVER on a signal (net, pin, whatever) it does
not represent a new net (which is what you're trying to do without luck with
your 'pad_ipd' signal...dump it.

Also note that since 'pad' is pulled up than it is not an 'input', the
device is actively driving that pin (albeit weakly) which makes it an I/O so
the use of 'inout' in the VHDL model is entirely accurate. Your definition
of 'pad' as an input only which you would like to drive with a pullup is
incorrect and is the reason you're having trouble with this problem.

Also note that having an entity to instantiate something that can be done by
adding one line of code is kinda pointless. Ask yourself which is clearer:
#1 or #2

#1 Some_Signal <= 'H'; -- Doing it the easy way.
#2: Pullup : entity work.inbuf port map(Some_Signal); -- Using your
entity

KJ

 

[ast]

"YK" <ykmayee@yahoo.com> a écrit dans le message de news: 1185568557.877163.151490@x35g2000prf.googlegroups.com...
On Jul 27, 10:15 am, "ast" <a...@ast.com> wrote:

"YK" <ykma...@yahoo.com> a écrit dans le message de news: 1185495755.824311.59...@k79g2000hse.googlegroups.com...





Hi

Is there a way to model a pullup on the input of a module without
using any internal signal like the verilog-HDL pullup.

If I model using a pullup map as below:

test_ipd <= pullupmap(TO_X01Z(test))

constant pullupmap : vitalresultzmaptype := ( 'X', 'X', '0', '1',
'H');

I can see that test_ipd is pulled up when test is 'Z'. But is it
possible to model such that pullup can be seen on "test" signal
instead of "test_ipd".

State H (weak high) of type std_logic- Hide quoted text -

- Show quoted text -

Thanks for your reply. Pardon me if I didn't understand the reply
correctly. Let me explain my problem in detail.

I am trying to write a simulation model for an input buffer with pull
up resistor. I want to model the pullup on the input port of a module,
not on the signal in the module.

The module is written below(didn't include the port delays and path
delays section)

entity inbuf is

port(PAD : in std_logic;
Yut std_logic);

end entity;

architecture buf_arch of inbuf is
pad_ipd : std_logic;
begin

pad_ipd <= 'H';
pad_ipd <= pad;
vitalbehavior : process(pad_ipd)--in this vitalpathdelay section is
not included
variable Y_zd : std_logic;
begin
Y_zd := TO_X01(pad_ipd);
end process

end buf_arch;


Now if the user simulates using this simulation model, he will able to
see the pullup on the pad_ipd signal only, not on the pad signal
directly. Again the pad_ipd is added just for user to be able to see
the pulledup input signal. Is there a way to show the pullup on "pad"
to the user.

--------
You dont see the pull up on PAD because in your model PAD is an "input" port.
PAD has to be an "inout" port according to me.

I would suggest the following code:

entity inbuf is

port(

PAD : inout std_logic;
Y ut std_logic);

end entity

architecture buf_arch of inbuf is
begin

PAD <= 'H';
Y <= TO_X01(PAD);

end buf_arch;