Modeling MOSFET Capacitance

[analog]

I am looking for hard information about the behavior of MOSFET
terminal capacitance as a function of both Vds and Vgs over the
full range of meaningful voltages. I am specifically interested
in good measured data over the range of Vgs from just under turn
on threshold to 10 or 15 volts negative. I have found only a few
sources on the net which attempt to address this although all of
these present only partial data. And I don't remember ever reading
a satisfactory journal article or conference paper about this either.

I recently translated the parameters contained within a subcircuit
based SPICE model (from the IR web site) to the proprietary, very
fast running LTspice VDMOS model statement (which specifically
accommodates the nonlinear Cdg capacitance). I then compared the
two modeling approaches and found they agreed quite well as long as
Vgs remained positive (to be fair, the LTspice help file warns that
its model is valid only for positive Vgs).

The IR subcircuit model seems as if it might be valid over a wider
range, but I can't really confirm this without more information
than is given on the typical MOSFET data sheet.

Anyone have any good pointers to more information on this subject?

Thanks. -- analog

PS: I could post the LTspice schematic file comparing the two models
if anyone is interested.

 

[Winfield Hill]

analog wrote...

I am looking for hard information about the behavior of MOSFET
terminal capacitance as a function of both Vds and Vgs over the
full range of meaningful voltages. I am specifically interested
in good measured data over the range of Vgs from just under turn
on threshold to 10 or 15 volts negative. I have found only a few
sources on the net which attempt to address this although all of
these present only partial data. And I don't remember ever reading
a satisfactory journal article or conference paper about this either.

I suspect it's not a very interesting issue, because probably
below 0V the gate capacitance changes only slightly.

Motorola became interested in a related issue a decade ago and
added positive Vgs variation to the characterization of their
TMOS family of FETs. Plots of Ciss and Crss vs. positive Vgs
(with Vd = 0V) still appear most ON Semi datasheets, e.g. see
the NTP60N06 and MTP2P50E, picked at random:
http://www.onsemi.com/pub/Collateral/NTP60N06-D.PDF
http://www.onsemi.com/pub/Collateral/MTP2P50E-D.PDF

While the gate capacitances we want are Cgs and Cgd, actual
FET measurements are Ciss = Cgs + Cgd (with ds shorted) and
Crss. Since Crss = Cgd, we have Cgs = Ciss - Cgd. Looking
at the curves in the data sheets above, we see that most of
the gate-capacitance variation with Vgs consists of the Cgd
portion. Sadly most of these plots are poorly drawn (and
badly measured, one discovers from his own measurements),
and likely cannot be replied upon to reveal bold new truths.
For example, small changes in the 0V location would have a
large impact in most of these plots.

Here's an especially interesting plot, if one can believe
it, http://www.onsemi.com/pub/Collateral/MTP10N60E7-D.PDF

Examining dozens of plots, one finds Ciss increases about
10 to 30% with Vgs from 0 to +10V, and that changes in Cgd
are primarily responsible. Not that it would matter much
when Vd is clamped at 0V. But in switching circuits Vd is
not suddenly 0V when the gate goes positive. Among other
things, the drain voltage has to change first. And there's
the famous Cgd Miller capacitance that must be charged with
the gate drive. A simple analysis of gate capacitance does
poorly in this scene, that's why we use gate-charge plots
instead. These deal directly with gate-voltage changes.

The highly-useful nature of gate-charge plots removed any
incentive other FET manufacturers may have had to follow
Motorola and add gate-voltage capacitance-plots.

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Russell Shaw]

Winfield Hill wrote:

analog wrote...

I am looking for hard information about the behavior of MOSFET
terminal capacitance as a function of both Vds and Vgs over the
full range of meaningful voltages. I am specifically interested
in good measured data over the range of Vgs from just under turn
on threshold to 10 or 15 volts negative. I have found only a few
sources on the net which attempt to address this although all of
these present only partial data. And I don't remember ever reading
a satisfactory journal article or conference paper about this either.


I suspect it's not a very interesting issue, because probably
below 0V the gate capacitance changes only slightly.

Motorola became interested in a related issue a decade ago and
added positive Vgs variation to the characterization of their
TMOS family of FETs. Plots of Ciss and Crss vs. positive Vgs
(with Vd = 0V) still appear most ON Semi datasheets, e.g. see
the NTP60N06 and MTP2P50E, picked at random:
http://www.onsemi.com/pub/Collateral/NTP60N06-D.PDF
http://www.onsemi.com/pub/Collateral/MTP2P50E-D.PDF

While the gate capacitances we want are Cgs and Cgd, actual
FET measurements are Ciss = Cgs + Cgd (with ds shorted) and
Crss. Since Crss = Cgd, we have Cgs = Ciss - Cgd. Looking
at the curves in the data sheets above, we see that most of
the gate-capacitance variation with Vgs consists of the Cgd
portion. Sadly most of these plots are poorly drawn (and
badly measured, one discovers from his own measurements),
and likely cannot be replied upon to reveal bold new truths.
For example, small changes in the 0V location would have a
large impact in most of these plots.

Here's an especially interesting plot, if one can believe
it, http://www.onsemi.com/pub/Collateral/MTP10N60E7-D.PDF

Examining dozens of plots, one finds Ciss increases about
10 to 30% with Vgs from 0 to +10V, and that changes in Cgd
are primarily responsible. Not that it would matter much
when Vd is clamped at 0V. But in switching circuits Vd is
not suddenly 0V when the gate goes positive. Among other
things, the drain voltage has to change first. And there's
the famous Cgd Miller capacitance that must be charged with
the gate drive. A simple analysis of gate capacitance does
poorly in this scene, that's why we use gate-charge plots
instead. These deal directly with gate-voltage changes.

The highly-useful nature of gate-charge plots removed any
incentive other FET manufacturers may have had to follow
Motorola and add gate-voltage capacitance-plots.

I've done GenRad bridge measurements on mosfet capacitance and
found the curves can be much more complex than those graphs
show, especially when done over the range of the three
terminal voltages. Spice is hardly a simulator (for active
devices anyway). It's more of an approximator. Real simulators
are finite-element things.

 

[Winfield Hill]

Russell Shaw wrote...

Winfield Hill wrote:
The highly-useful nature of gate-charge plots removed any
incentive other FET manufacturers may have had to follow
Motorola and add gate-voltage capacitance-plots.

I've done GenRad bridge measurements on mosfet capacitance
and found the curves can be much more complex than those
graphs show, especially when done over the range of the three
terminal voltages. Spice is hardly a simulator (for active
devices anyway). It's more of an approximator. Real simulators
are finite-element things.

I agree that measurements of real devices show different data
and reveal fascinating aspects that're missing from data-sheet
plots. I discovered this when measuring high-voltage FETs at
1MHz with my HP 4274 capacitance meter. What one sees in real
FETs that's missing from data sheets is a dramatic capacitance
change just above the gate linear-region turned-on voltage.

Can spice can be made to match the real data? Some spice models
actually do very well, if evaluated on a gate-charge basis. The
innovative FET model developed by CF Wheatley and HR Ronan (with
a depletion-mode JFET) is claimed to closely match real parts.
If interested, read Fairchild's modern reprint of the venerable
RCA research: http://www.fairchildsemi.com/an/AN/AN-7506.pdf

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Mike Engelhardt]

Analog, Win,

I am looking for hard information about the behavior of MOSFET
terminal capacitance as a function of both Vds and Vgs over the
full range of meaningful voltages. I am specifically interested
in good measured data over the range of Vgs from just under turn
on threshold to 10 or 15 volts negative. I have found only a few
sources on the net which attempt to address this although all of
these present only partial data. And I don't remember ever reading
a satisfactory journal article or conference paper about this either.

I suspect it's not a very interesting issue, because probably
below 0V the gate capacitance changes only slightly.

I checked a coupled VDMOS power FETs at negative gates and found,
as I recall, about 20% change in capacitance when varied down to
-15V. It's a trivial measurement because the FET is off, so any
old component analyzer that can supply a bias can do the job. I
left the ability to vary Gate-Source capacitance in the the VDMOS
transistor in LTspice out as a matter of my engineering
sensibilities. The action is in that very non-linear Gate-Drain
capacitance which is so qualitatively different than the monolithic
MOSFETs of ICs. This Miller capacitance dominates the device's
switching behavior in many applications with practical gate drive
impedances.

(to be fair, the LTspice help file warns that
its model is valid only for positive Vgs).

I put that comment there because I met a blue hair who insisted
there was some action down there. He was thinking of monolithic
MOSFETs, not vertical doubly defused ones. At the time it was
easier to simply point out that that capacitance is taken as
constant than explain to him how vertical doubly defused MOSFETs
are constructed.

--Mike

 

[analog]

Winfield Hillh wrote:

Russell Shaw wrote:
Winfield Hill wrote:

The highly-useful nature of gate-charge plots removed any
incentive other FET manufacturers may have had to follow
Motorola and add gate-voltage capacitance-plots.

I've done GenRad bridge measurements on mosfet capacitance
and found the curves can be much more complex than those
graphs show, especially when done over the range of the three
terminal voltages. Spice is hardly a simulator (for active
devices anyway). It's more of an approximator. Real simulators
are finite-element things.

The last paper cited below has some multidimensional data which
illuminates the 3-d nature of mosfet capacitance. Perhaps some
of the other papers do as well (haven't got them all yet).

A topographical colored, 3-d style plot with Vds and Vgs as the
x and y axes and capacitance in the z direction would be nice to
find. I wonder if anyone ever has taken enough data and plotted
it this way?

I agree that measurements of real devices show different data
and reveal fascinating aspects that're missing from data-sheet
plots. I discovered this when measuring high-voltage FETs at
1MHz with my HP 4274 capacitance meter. What one sees in real
FETs that's missing from data sheets is a dramatic capacitance
change just above the gate linear-region turned-on voltage.

Can spice can be made to match the real data? Some spice models
actually do very well, if evaluated on a gate-charge basis. The
innovative FET model developed by CF Wheatley and HR Ronan (with
a depletion-mode JFET) is claimed to closely match real parts.
If interested, read Fairchild's modern reprint of the venerable
RCA research: http://www.fairchildsemi.com/an/AN/AN-7506.pdf

Your prior links to data sheets with extensive capacitance plots:

http://www.onsemi.com/pub/Collateral/NTP60N06-D.PDF
http://www.onsemi.com/pub/Collateral/MTP2P50E-D.PDF
http://www.onsemi.com/pub/Collateral/MTP10N60E7-D.PDF [the weird one]
------
This paper has some Ciss curves that resemble the weird one above:

"Advanced Unified Lateral DMOS Transistor Model for Automotive Circuit
Simulation, PROTOTYPE OF MACRO MODEL"

http://www.automacs.org/D2%20web.pdf
------
The authors are unnamed, but this paper appears to be from the
Wheatley and Ronan group:

"A New PSPICE Subcircuit for the Power MOSFET Featuring Global
Temperature Options"

http://www.fairchildsemi.com/an/AN/AN-7510.pdf
------
From a extended search of the IEEE explore abstracts (these papers
are available online as pdf's at many university libraries):

"An improved power MOSFET macro model for SPICE simulation", Jia, J.,
CAD of Power Electronic Circuits, IEE Colloquium on, Vol., Iss.,
9 Apr 1992, Pages:3/1-3/8

"Empirical power MOSFET modeling: practical characterization and
simulation implantation", Verneau, G.; Aubard, L.; Crebier, J.-C.;
Schaeffer, C.; Schanen, J.-L., Industry Applications Conference, 2002.
37th IAS Annual Meeting. Conference Record of the, Vol.4, Iss., 2002,
Pages: 2425-2432 vol.4

"Power MOSFET switching waveforms: an empirical model based on a
physical analysis of charge locations", Aubard, L.; Verneau, G.;
Crebier, J.C.; Schaeffer, C.; Avenas, Y., Power Electronics
Specialists Conference, 2002. pesc 02. 2002 IEEE 33rd Annual, Vol.3,
Iss., 2002, Pages: 1305-1310 vol.3

"A new physical power MOSFET model for improved simulation in power
electronic design", Victory, J.; Miller, I.; Sanchez, J.; DeMassa,
T.; Welfert, B., Power Electronics in Transportation, 1994.
Proceedings, Vol., Iss., 20-21 Oct 1994, Pages:83-90

"The lumped-charge power MOSFET model, including parameter
extraction", Budihardjo, I.; Lauritzen, P.G., Power Electronics,
IEEE Transactions on, Vol.10, Iss.3, May 1995, Pages:379-387

"Performance requirements for power MOSFET models", Budihardjo, I.K.;
Lauritzen, P.O.; Mantooth, H.A., Power Electronics, IEEE Transactions
on, Vol.12, Iss.1, Jan 1997, Pages:36-45
------

Perhaps I will stop by the university next weekend so I can dig through
all of these papers and muse over what sort of not-too-complicated,
but capacitively accurate, extended behavioral MOSFET model might be
appropriate for LTspice.

 

[Russell Shaw]

Winfield Hill wrote:

Russell Shaw wrote...

Winfield Hill wrote:

The highly-useful nature of gate-charge plots removed any
incentive other FET manufacturers may have had to follow
Motorola and add gate-voltage capacitance-plots.

I've done GenRad bridge measurements on mosfet capacitance
and found the curves can be much more complex than those
graphs show, especially when done over the range of the three
terminal voltages. Spice is hardly a simulator (for active
devices anyway). It's more of an approximator. Real simulators
are finite-element things.

I agree that measurements of real devices show different data
and reveal fascinating aspects that're missing from data-sheet
plots. I discovered this when measuring high-voltage FETs at
1MHz with my HP 4274 capacitance meter. What one sees in real
FETs that's missing from data sheets is a dramatic capacitance
change just above the gate linear-region turned-on voltage.

Can spice can be made to match the real data? Some spice models
actually do very well, if evaluated on a gate-charge basis. The
innovative FET model developed by CF Wheatley and HR Ronan (with
a depletion-mode JFET) is claimed to closely match real parts.
If interested, read Fairchild's modern reprint of the venerable
RCA research: http://www.fairchildsemi.com/an/AN/AN-7506.pdf

I can hardly remember the charge-based mosfet modelling used in
spice when i studied it, but from memory, it was very simplistic.

Spice will probably *never* have accurate models for the more
loopy curves. Embedding the basic device into a subcircuit is
probably the only way to add more effects.

The basic problem is that real simulators such as a 2D semiconductor
field simulator give accurate results for *one* point in time, or
are run for a long time to get a limited number of time points
such as for a transient response.

Spice needs to use numerically fast (and hence simpler) models
for quickly calculating hundreds or thousands of time points.
For this reason, users need to learn the limitations of spice
and use it more as a verification tool rather than assuming
that just because they have spice, they don't need to know
the full details of the circuit they're trying to get work
(i won't say design, because that's not what's happening).
What's more, users should recognize limited and bogus spice
models floating around as free downloads.

 

[Bill Sloman]

"Mike Engelhardt" <pmte@concentric.net> wrote in message news:<btvmhh$jib@dispatch.concentric.net>...

Analog, Win,

I am looking for hard information about the behavior of MOSFET
terminal capacitance as a function of both Vds and Vgs over the
full range of meaningful voltages. I am specifically interested
in good measured data over the range of Vgs from just under turn
on threshold to 10 or 15 volts negative. I have found only a few
sources on the net which attempt to address this although all of
these present only partial data. And I don't remember ever reading
a satisfactory journal article or conference paper about this either.

I suspect it's not a very interesting issue, because probably
below 0V the gate capacitance changes only slightly.

I checked a coupled VDMOS power FETs at negative gates and found,
as I recall, about 20% change in capacitance when varied down to
-15V. It's a trivial measurement because the FET is off, so any
old component analyzer that can supply a bias can do the job. I
left the ability to vary Gate-Source capacitance in the the VDMOS
transistor in LTspice out as a matter of my engineering
sensibilities. The action is in that very non-linear Gate-Drain
capacitance which is so qualitatively different than the monolithic
MOSFETs of ICs. This Miller capacitance dominates the device's
switching behavior in many applications with practical gate drive
impedances.

(to be fair, the LTspice help file warns that
its model is valid only for positive Vgs).

I put that comment there because I met a blue hair who insisted
there was some action down there. He was thinking of monolithic
MOSFETs, not vertical doubly defused ones. At the time it was
easier to simply point out that that capacitance is taken as
constant than explain to him how vertical doubly defused MOSFETs
are constructed.

Much though I like the idea of a fuzed MOSFET, which would presumably
prevent the fusion of the active areas under persistent overload, an
operation which might have been reversed in a defused MOSFET (if you
had been very lucky), I think you meant double diffused MOSFETs, where
the diffusion refers to the introduction of dopants into the silicon
by solid-state diffusion at relatively high temperatures

Dyslexia lures!

-------
Bill Sloman, Nijmegen

 

[Mike Engelhardt]

Bill,

vertical doubly defused MOSFETs

... I think you meant double diffused MOSFETs...

Yes, of course I meant double-diffused vertical MOSFET's --
not defused, just like I wrote in the released VDMOS
documentation of LTspice. Fortunately here in Usenet often
some asshole around to correct one's copy, even for bi-
illiterate[*] people like me. Thanks for reading.

--Mike

*] People who can't read and write in two languages.