Modeling large memories in Verilog

[TMU]

hello all


can anyone help me?


I want to model large memories in verilog.But you know that for
modeling for example 1M RAM memory about 32M in system is requierd.


so it will be fine if we could model the RAM elements in PLI.


can anyone help me for writing or finding such PLI?
with very best wishes

 

[Berty]

I assume while you have 1M you plan only to write and read from
"few" of those address and if so why not using smaller amount of
memory with some logic to get associative memory which will look
outside as 1M but will actually be let say 1K.
Of course the "disadvantage" is that you can't write more than 1K
entries (Or what ever size you decide to use.).

Have fun.

 

[raul]

Hi,

If your intention is simulating and use ModelSim PE 6.0c on Windows XP,
there is much less overhead than what you mention when simulating
memory.

I recently simulated 128MB of memory (declaring a register array of 128
MB) with only about 150 MB of additional run-time program size.

 

[Swapnajit Mittra]

My book 'Principles of Verilog PLI' contains an example of how to model
virtual memories using Verilog PLI (see Chapter 6). You can buy it from
here (look at the 'Featured Books' section):

<URL: http://www.project-veripage.com/books.php>

There are also other ways of modeling large memories that are available
from commercial simulator vendors.

- Swapnajit.