Modeling a serial port in Verilog.

Hi All,
I need to develop a serial port model (with most of the functionalities
such as adjustable data width, parity, number of stop bits etc) in
Verilog. Could anyone of you guide me towards any good links for the
same ?

Thanks in advance,
Amit.

 

I need to develop a serial port model (with most of the functionalities
such as adjustable data width, parity, number of stop bits etc) in
Verilog. Could anyone of you guide me towards any good links for the
same ?

Thanks in advance,

There's a lot of information here: http://google.com/

 

[gabor]

MikeShepherd...@btinternet.com wrote:

I need to develop a serial port model (with most of the functionalities
such as adjustable data width, parity, number of stop bits etc) in
Verilog. Could anyone of you guide me towards any good links for the
same ?

Thanks in advance,

There's a lot of information here: http://google.com/

or better:

http://www.opencores.org/browse.cgi/by_category

 

Couldn't get any relevant links in the top 20 results.

-A.

 

Thanks a lot Gabor.

-Amit.

 

Couldn't get any relevant links in the top 20 results.

-A.

Just post your query again in this group. After all, that's what
we're here for - to look through all those Google pages for you when
you get tired after the first two.

 

Just post your query again in this group. After all, that's what
we're here for - to look through all those Google pages for you when
you get tired after the first two.

Sincere apologies Mike,
Henceforth, I shall be really, *really* careful and will first do my
homework before posting a query.

Sorry again.

Have a nice day.
Amit.

 

[Rob]

You could also go to opencores.org and see a real example.


<amitsheth@gmail.com> wrote in message
news:1147183169.804791.49620@u72g2000cwu.googlegroups.com...

Hi All,
I need to develop a serial port model (with most of the functionalities
such as adjustable data width, parity, number of stop bits etc) in
Verilog. Could anyone of you guide me towards any good links for the
same ?

Thanks in advance,
Amit.

 

Rob wrote:

You could also go to opencores.org and see a real example.

Hi Rob,
Thanks a lot. I already checked out opencores.org and the material in
there is indeed good.

Regards,
Amit.

 

[Andy Peters]

amitsheth@gmail.com wrote:

Couldn't get any relevant links in the top 20 results.

How about searching for "Verilog UART" ?

-a

 

Andy Peters wrote:

How about searching for "Verilog UART" ?

Hi Andy,
Many thanks for your help.

Regards,
Amit.