Modeling a quantiser in VHDL (synthesisable circuit)

[vishallko31@gmail.com]

Hi

I am trying to model a quantizer for Digital PLL. What I have to do is
something like this:

I get a xor_pulse (which is indicative of the phase difference between
input and output) frequency of PLL. I need to quantise this pulse in
steps of 50 ps.

The standard library (65 nm) that I am using has buffers whose delay
varies from 19 to 50 ps (best and worst process).

Now what I am doing is: I model a delay line. I instantiate 95 buffers
(95 is the largest word that I would get) in a chain. I feed xor_pulse
to this and chain and the progressively delayed xor_pulses are used as
clocks to my flip-flops. The xor_pulse is fed to the D input of these
flip flops. I tested this by simulating the circuit and it worked
alright.

The trouble is: Xor_pulse goes to 95 flip flops...

1) i want that xor_pulse should not drive more than 2 cells....i want
to limit the loading....
2) Xor_pulse should reach all the flip flops (D pin) at the same
time....

what should I do to acheive the above two requirement....

somebody please advice....

regards
Vishal