J
jjsandoval1962@aol.com
Guest
Hi All,
I am currently helping some DSP and FPGA engineers with their verilog
test-bench verification environment (I am a logic designer and not a
verification person). What they have is a wireless design composed
mostly of a MAC and baseband blocks. The challenge has been testing
the receiver side of the baseband which is composed of various large
DSP blocks. The symbols on the receiver side are mapped to in-phase, I,
and quadrature, Q, components for QPSK encoding, so the inputs to the
baseband receiver are IQ type signals from the ADC devices. I have
been able to put a test-bench where I generate transmitter data, dump
the transmitted data into a file, and feed that same file to the
receiver and check against expected results. Essentially using the
transmitter to test the receiver. This has worked so far, although I am
limited to sending ideal (non-corrupted data). I am sure there is a
better way. I am thinking that the DSP guys could come up with a IQ
generator model (created in their Matlab tool) that would allow me to
introduce all those little exceptions that would really test the design
(noise, bit corruption, etc). Although I am not sure how I would marry
this Matlab model to my verilog test-bench.
Is anyone out there testing something similar. What methodology are
you using for this type of scenario?
Any feedback is greatly appreciated.
Jose
I am currently helping some DSP and FPGA engineers with their verilog
test-bench verification environment (I am a logic designer and not a
verification person). What they have is a wireless design composed
mostly of a MAC and baseband blocks. The challenge has been testing
the receiver side of the baseband which is composed of various large
DSP blocks. The symbols on the receiver side are mapped to in-phase, I,
and quadrature, Q, components for QPSK encoding, so the inputs to the
baseband receiver are IQ type signals from the ADC devices. I have
been able to put a test-bench where I generate transmitter data, dump
the transmitted data into a file, and feed that same file to the
receiver and check against expected results. Essentially using the
transmitter to test the receiver. This has worked so far, although I am
limited to sending ideal (non-corrupted data). I am sure there is a
better way. I am thinking that the DSP guys could come up with a IQ
generator model (created in their Matlab tool) that would allow me to
introduce all those little exceptions that would really test the design
(noise, bit corruption, etc). Although I am not sure how I would marry
this Matlab model to my verilog test-bench.
Is anyone out there testing something similar. What methodology are
you using for this type of scenario?
Any feedback is greatly appreciated.
Jose