A
Andy Luotto
Guest
Hi there
I am going to design a behavioural model which check set and hold on a
sinchronous interface.
The way to go should be aspecify block with specparams and $setiup,
$hold et etc
specify
specparam
tHI = 600, // SCL pulse width - high
tLO = 1300, // SCL pulse width - low
tSU_STA = 600, // SCL to SDA setup time
tHD_STA = 600, // SCL to SDA hold time
tSU_DAT = 100, // SDA to SCL setup time
tSU_STO = 600; // SCL to SDA setup time
$width (posedge SCL, tHI);
$width (negedge SCL, tLO);
$setup (SCL, negedge SDA &&& TimingCheckEnable, tSU);
Change the timing parameters with SDF backannotation works fine: waht
about passing timing parmateres as module parameters, i.e. not using
backannotion?
Is it possible? I cannot find a way for this
Thanks
I am going to design a behavioural model which check set and hold on a
sinchronous interface.
The way to go should be aspecify block with specparams and $setiup,
$hold et etc
specify
specparam
tHI = 600, // SCL pulse width - high
tLO = 1300, // SCL pulse width - low
tSU_STA = 600, // SCL to SDA setup time
tHD_STA = 600, // SCL to SDA hold time
tSU_DAT = 100, // SDA to SCL setup time
tSU_STO = 600; // SCL to SDA setup time
$width (posedge SCL, tHI);
$width (negedge SCL, tLO);
$setup (SCL, negedge SDA &&& TimingCheckEnable, tSU);
Change the timing parameters with SDF backannotation works fine: waht
about passing timing parmateres as module parameters, i.e. not using
backannotion?
Is it possible? I cannot find a way for this
Thanks