model sim errors in my design

[srinukasam]

Hello
In my design i need to assign part of std_logic_vector to array that I
deifined.
I wrote program and test bench for that. With model sim at the time of
compilation no errors with my design, but at the time of simulation its
showing some errors. Please guide me about errors.

ERRORS :
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__5
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__5
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__4
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__4
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__3
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__3
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__2
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__2
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__0
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_gene_tb/mut/ge__0
# ** Fatal: (vsim-3421) Index 27 is out of range 23 downto 0.
# Time: 4 ns Iteration: 0 Process: /mux_gene_tb/mut/sort File:
/disk/users2/kasam/hds_projects/Controller/controller/hdl/mux_gene_mux_gene_beh.vhd

DESIGN:--------------------------------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.contr_pak.all;

ENTITY mux_gene IS

generic ( size :integer :=16; --input signal width
ictrl_width :integer :=4; -- individual control signal
width
tctrl_width : integer :=24; -- total control signal
width--mem out
no_out,no_ctrl :integer :=6); -- no of output
signals(r),no.of control signals (V)

port(clk : in std_logic;
input : in std_logic_vector( size-1 downto 0);
ctrl : in std_logic_vector( tctrl_width-1 downto 0);
mux_out : out std_logic_vector(no_out-1 downto 0));
END ENTITY mux_gene;
--
ARCHITECTURE mux_gene_beh OF mux_gene IS
type ctrl_gen is array(integer range <&gt of std_logic_vector(0 to
ictrl_width-1);
signal ctrl_arr : ctrl_gen(0 to (2**no_ctrl)-1);
signal z : out_gen;

BEGIN
sortrocess(ctrl)
variable first:integer:=0;
variable second:integer:=0;
variable temp :std_logic_vector(ictrl_width-1 downto 0);
begin
for i in 0 to no_ctrl-1 loop
if i=0 then
ctrl_arr(i) <=ctrl(ictrl_width-1 downto 0);
else
first:=first+ictrl_width;
second:=first+(ictrl_width-1);
temp:= ctrl(second downto first); -- here is the source code error
according to model sim.
ctrl_arr(i) <= temp;
end if;
end loop;
--wait;
end process sort;
ge:for i in 0 to no_out-1 generate
z(i) <=input(conv_integer(ctrl_arr(i)));
end generate ge;

oprocess(z,clk)
begin
if clk'event and clk='1' then
for i in 0 to no_out-1 loop
mux_out(i)<=z(i);
end loop;
end if;
end process op;
--end if;

END ARCHITECTURE mux_gene_beh;

TB:signals---------------------------------------------------------------------------------------------------------

stimuli: process
begin
clk<= '0','1' after 5 ns, '0' after 10 ns,
'1' after 15 ns, '0' after 20 ns,
'1' after 25 ns, '0' after 30 ns,
'1' after 35 ns, '0' after 40 ns,
'1' after 45 ns, '0' after 50 ns,
'1' after 55 ns, '0' after 60 ns,
'1' after 65 ns, '0' after 70 ns,
'1' after 75 ns, '0' after 80 ns;

input<="0000000000000000" after 4 ns,
"1111111111111111" after 14 ns,
"0000000011111111" after 24 ns,
"1111111100000000" after 34 ns,
"1111000011110000" after 44 ns,
"0000111100001111" after 54 ns;

ctrl<="000000010010001101000101" after 4 ns,
"011001111000100111001101" after 14 ns,
"000100110101011110011101" after 24 ns,
"000000100100011010001100" after 34 ns,
"111110101110100101110000" after 44 ns,
"000001010111100100111101" after 54 ns;

wait;
end process stimuli;

controlrocess
begin
wait for 5 ns;
assert(mux_out="000000")report "z is false at 5 ns" severity
failure;
wait for 10 ns;
assert(mux_out="111111")report "z is false at 15 ns" severity
failure;
wait for 10 ns;
assert(mux_out="001111")report "z is false at 25 ns" severity
failure;
wait for 10 ns;
assert(mux_out="110000")report "z is false at 35 ns" severity
failure;
wait for 10 ns;
assert(mux_out="101010")report "z is false at 45 ns" severity
failure;
wait for 10 ns;
assert(mux_out="100111")report "z is false at 55 ns" severity
failure;

wait;
end process control;

 

[Ralf Hildebrandt]

srinukasam wrote:

I wrote program and test bench for that. With model sim at the time of
compilation no errors with my design, but at the time of simulation its
showing some errors. Please guide me about errors.

ERRORS :
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).

This is a warning - not an error. You are converting something to
integer, that is at this moment 'U', 'X', 'W', 'Z' or '-'. At simulation
start all signals are uninitialized and therefore it is quite normal to
have this conversion problem before reset.

Nevertheless, these warnings are annoying. Sometimes you can get rid of
them: If your purpose of converting a signal to integer is easier test
of the signal against a value, then it is better to convert the value to
another type instead. Example:

if ( 123 > to_integer(unsigned(my_std_ulogic_vector)) ) then -- bad

if ( to_unsigned(123, my_std_ulogic_vector'length) >
unsigned(my_std_ulogic_vector) ) then -- good

In the 2nd case no conversion to integer takes place and therefore no
such warning will appear. Note, that both cases result in the same hardware.

# ** Fatal: (vsim-3421) Index 27 is out of range 23 downto 0.
# Time: 4 ns Iteration: 0 Process: /mux_gene_tb/mut/sort File:
/disk/users2/kasam/hds_projects/Controller/controller/hdl/mux_gene_mux_gene_beh.vhd

O.k. - this is the only real problem. You are reading / writing to an
element outside the bounds of the vector.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

<prayer wheel>
You don't want to use std_logic_arith or std_logic_unsigned, because
they are not standard libraries
Take ieee.numeric_std.all!
</prayer wheel>

Ralf