model sim error in my design

[srinukasam]

hi
i created a memory like below.and i wrote test bench for that.while doing
simulaton with model sim its giving the error..like below..

Fatal: (vsim-3421) Value -97 is out of range 0 to 255.
# Time: 25 ns Iteration: 0 Process: /mux_mem_tb/mut/line__44 File:
/disk/users2/kasam/hds_projects/Controller/controller/hdl/mux_mem_mux_mem_beh.vhd

AND MY TEST VECTORS ARE LIKE THIS
clk<= '0','1' after 5 ns, '0' after 10 ns,
'1' after 15 ns, '0' after 20 ns,
'1' after 25 ns, '0' after 30 ns,
'1' after 35 ns, '0' after 40 ns,
'1' after 45 ns, '0' after 50 ns,
'1' after 55 ns, '0' after 60 ns,
'1' after 65 ns, '0' after 70 ns,
we<='1' after 4 ns, '0' after 7 ns,
'1' after 24 ns, '0' after 27 ns,
'1' after 34 ns, '0' after 37 ns;

w_addr<= "00000000" after 4 ns,
"10011111" after 24 ns,
"00001111" after 34 ns;

re<='1' after 14 ns, '0' after 17 ns,
'1' after 44 ns, '0' after 47 ns,
'1' after 54 ns, '0' after 57 ns;

r_addr<= "00000000" after 14 ns,
"10011111" after 44 ns,
"00001111" after 54 ns;

data_in <= "000000000000111111111111" after 4 ns,
"111111111111000000000000" after 24 ns,
"111111000000111111000000" after 34 ns;

reset<='1' after 20 ns, '0'after 23 ns;



DESIGN STARTS HERE------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use work.contr_pak.all;

ENTITY mux_mem IS
generic(addr_width: integer:=8;
data_width: integer :=24);

port(
clk : in std_logic;
reset : in std_logic;
w_addr : in std_logic_vector(addr_width-1 downto 0); --write
address (state bits)
r_addr : in std_logic_vector(addr_width-1 downto 0); -- read
address (state bits)
data_in : in std_logic_vector(data_width-1 downto 0); -- input
dara
data_out : out std_logic_vector(data_width-1 downto 0);
--output data ( input ctrl width

-- incl..no )
we : in std_logic;
re : in std_logic);
END ENTITY mux_mem;

--
ARCHITECTURE mux_mem_beh OF mux_mem Is
type mux_mem is array (integer range <&gt of std_logic_vector(data_width-1
downto 0);
signal ram1: mux_mem(0 to (2**addr_width)-1);

begin

process(clk,reset)
begin

if reset = '1' then
data_out <=(others=>'0');

elsif clk'event and clk='1' then
if re = '1' then
data_out <= ram1(conv_integer(r_addr));
-- data_out<= ram1(vect_to_int(r_addr));
--else
-- data_out <= (others=>'0');
end if;

if we = '1' then
ram1(conv_integer(w_addr))<= data_in;
--ram1(vect_to_int(w_addr)) <= data_in;
end if;
end if;

end process;

END ARCHITECTURE mux_mem_beh;


COULD PLS MAIL EM SOME SUGGATIONS FOR MY PROB::
THANK YOU