model sim block ram sim

Guest
Hi -

I am trying to run a very simple simulation to verify the functionality of
the "block ram" component in my spartan ii fpga. I am using modelsim
tools that I downloaded from the xilinx website, and I'm using the
"ramb4_s8" primitive. The simulation appears to work properly except that
there appears to be a delay of one clock cycle when reading from the
memory. In other words, if I enable the ram, deassert the write enable,
and select the read address, I need TWO rising clock edges to get the
correct data to appear at the data_out port. I am doing a simple
behavioral simulation so there shouldn't be any delay issues involved.
The data sheet clearly shows that I should only need one rising clock edge
to execute the read. Any ideas? Thanks very much!!!

--Iyad

-------------------------------
Iyad Obeid
Dept. of Biomedical Engineering
Duke University
io@duke.edu
(919)660-5104 www.duke.edu/~io
 
io@duke.edu wrote:
Hi -

I am trying to run a very simple simulation to verify the functionality of
the "block ram" component in my spartan ii fpga. I am using modelsim
tools that I downloaded from the xilinx website, and I'm using the
"ramb4_s8" primitive. The simulation appears to work properly except that
there appears to be a delay of one clock cycle when reading from the
memory. In other words, if I enable the ram, deassert the write enable,
and select the read address, I need TWO rising clock edges to get the
correct data to appear at the data_out port. I am doing a simple
behavioral simulation so there shouldn't be any delay issues involved.
The data sheet clearly shows that I should only need one rising clock edge
to execute the read. Any ideas? Thanks very much!!!

--Iyad

-------------------------------
Iyad Obeid
Dept. of Biomedical Engineering
Duke University
io@duke.edu
(919)660-5104 www.duke.edu/~io
Click to expand...
Maybe you need to register the address.
http://groups.google.com/groups?q=sync_ram+entity+lpm_ram_dq

-- Mike Treseler
 
In Virtex BlockRAMs nothing happens without being instigated by a clock
edge. That's why they are called synchronous RAMs.
Peter Alfke

Jim Wu wrote:
My apologies if it is too obvious, but did you count the clock cycle
that sets up the read address as one of the TWO clock cycles?

If you can post your code or waveform, that would be helpful.

Jim Wu
jimwu88NOOOOOSPAM@yahoo.com

io@duke.edu wrote in message news:<Pine.GSO.4.56.0308051041170.29999@hudson11.acpub.duke.edu>...
Hi -

I am trying to run a very simple simulation to verify the functionality of
the "block ram" component in my spartan ii fpga. I am using modelsim
tools that I downloaded from the xilinx website, and I'm using the
"ramb4_s8" primitive. The simulation appears to work properly except that
there appears to be a delay of one clock cycle when reading from the
memory. In other words, if I enable the ram, deassert the write enable,
and select the read address, I need TWO rising clock edges to get the
correct data to appear at the data_out port. I am doing a simple
behavioral simulation so there shouldn't be any delay issues involved.
The data sheet clearly shows that I should only need one rising clock edge
to execute the read. Any ideas? Thanks very much!!!

--Iyad

-------------------------------
Iyad Obeid
Dept. of Biomedical Engineering
Duke University
io@duke.edu
(919)660-5104 www.duke.edu/~io
Click to expand...
 
I assert the read address on the falling edge of the clock. On the first
rising edge that follows, I expect to see the data stored at that read
address, but instead i have to wait for the second rising clk edge to see
it.

The vhdl code is below. The waveforms are at www.duke.edu/~io/wave.jpg

Thank you!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.constants.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity ramtest is

port (
we : in std_logic;
en : in std_logic;
rst : in std_logic;
clk : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0));

end ramtest;

architecture xilinx of ramtest is

component RAMB4_S8
port (
WE : IN STD_LOGIC;
EN : IN STD_LOGIC;
RST : IN STD_LOGIC;
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;

begin -- xilinx

R0 : RAMB4_S8 port map (
WE => we,
EN => en,
RST => rst,
CLK => clk,
ADDR => addr,
DI => di,
DO => do);


end xilinx;


On Tue, 5 Aug 2003, Jim Wu wrote:

My apologies if it is too obvious, but did you count the clock cycle
that sets up the read address as one of the TWO clock cycles?

If you can post your code or waveform, that would be helpful.

Jim Wu
jimwu88NOOOOOSPAM@yahoo.com

io@duke.edu wrote in message news:<Pine.GSO.4.56.0308051041170.29999@hudson11.acpub.duke.edu>...
Hi -

I am trying to run a very simple simulation to verify the functionality of
the "block ram" component in my spartan ii fpga. I am using modelsim
tools that I downloaded from the xilinx website, and I'm using the
"ramb4_s8" primitive. The simulation appears to work properly except that
there appears to be a delay of one clock cycle when reading from the
memory. In other words, if I enable the ram, deassert the write enable,
and select the read address, I need TWO rising clock edges to get the
correct data to appear at the data_out port. I am doing a simple
behavioral simulation so there shouldn't be any delay issues involved.
The data sheet clearly shows that I should only need one rising clock edge
to execute the read. Any ideas? Thanks very much!!!

--Iyad

-------------------------------
Iyad Obeid
Dept. of Biomedical Engineering
Duke University
io@duke.edu
(919)660-5104 www.duke.edu/~io
Click to expand...
-------------------------------
Iyad Obeid
Dept. of Biomedical Engineering
Duke University
io@duke.edu
(919)660-5104 www.duke.edu/~io
 
Here is what should work:
You decide on a clock edge (polarity), either rising or falling.
Right before this clock edge ( set-up time is very short, about 1 ns)
you must have valid address and valid clock enable and Read/write control.
A few nanoseconds ( 3ns?) after this clock edge you see the data on the
Dout lines.

If you do a write the same way, you will also always read the data that
you addressed. In Virtex-II you have a choice to read the old (previous)
data or the new data (the one you are just writing)

Set-up and hold times are extremely short: clock-to-out delay is
relatively long ( since it includes decoding and other delays).
Peter Alfke
===================
io@duke.edu wrote:
I assert the read address on the falling edge of the clock. On the first
rising edge that follows, I expect to see the data stored at that read
address, but instead i have to wait for the second rising clk edge to see
it.

The vhdl code is below. The waveforms are at www.duke.edu/~io/wave.jpg

Thank you!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.constants.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity ramtest is

port (
we : in std_logic;
en : in std_logic;
rst : in std_logic;
clk : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0));

end ramtest;

architecture xilinx of ramtest is

component RAMB4_S8
port (
WE : IN STD_LOGIC;
EN : IN STD_LOGIC;
RST : IN STD_LOGIC;
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;

begin -- xilinx

R0 : RAMB4_S8 port map (
WE => we,
EN => en,
RST => rst,
CLK => clk,
ADDR => addr,
DI => di,
DO => do);

end xilinx;

On Tue, 5 Aug 2003, Jim Wu wrote:

My apologies if it is too obvious, but did you count the clock cycle
that sets up the read address as one of the TWO clock cycles?

If you can post your code or waveform, that would be helpful.

Jim Wu
jimwu88NOOOOOSPAM@yahoo.com

io@duke.edu wrote in message news:<Pine.GSO.4.56.0308051041170.29999@hudson11.acpub.duke.edu>...
Hi -

I am trying to run a very simple simulation to verify the functionality of
the "block ram" component in my spartan ii fpga. I am using modelsim
tools that I downloaded from the xilinx website, and I'm using the
"ramb4_s8" primitive. The simulation appears to work properly except that
there appears to be a delay of one clock cycle when reading from the
memory. In other words, if I enable the ram, deassert the write enable,
and select the read address, I need TWO rising clock edges to get the
correct data to appear at the data_out port. I am doing a simple
behavioral simulation so there shouldn't be any delay issues involved.
The data sheet clearly shows that I should only need one rising clock edge
to execute the read. Any ideas? Thanks very much!!!

--Iyad

-------------------------------
Iyad Obeid
Dept. of Biomedical Engineering
Duke University
io@duke.edu
(919)660-5104 www.duke.edu/~io


-------------------------------
Iyad Obeid
Dept. of Biomedical Engineering
Duke University
io@duke.edu
(919)660-5104 www.duke.edu/~io
Click to expand...
 
Right you are. That solved the problem quite effectively. Thanks. I
usually use the default timing for my behavioral sims and I've never run
into this kind of issue before.

Thanks for your time, everyone.

--Iyad

On Tue, 5 Aug 2003, Brian Philofsky wrote:

It looks like you are running your clock at 10 GHz. There is a 100ps
propagation delay in the model but that is also your period you have
defined for your simulation clock. I suggest slowing down your clock to
a more realistic speed and that may improve things for you.

-- Brian


io@duke.edu wrote:
I assert the read address on the falling edge of the clock. On the first
rising edge that follows, I expect to see the data stored at that read
address, but instead i have to wait for the second rising clk edge to see
it.

The vhdl code is below. The waveforms are at www.duke.edu/~io/wave.jpg

Thank you!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.constants.all;

library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity ramtest is

port (
we : in std_logic;
en : in std_logic;
rst : in std_logic;
clk : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0));

end ramtest;

architecture xilinx of ramtest is

component RAMB4_S8
port (
WE : IN STD_LOGIC;
EN : IN STD_LOGIC;
RST : IN STD_LOGIC;
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;

begin -- xilinx

R0 : RAMB4_S8 port map (
WE => we,
EN => en,
RST => rst,
CLK => clk,
ADDR => addr,
DI => di,
DO => do);


end xilinx;


On Tue, 5 Aug 2003, Jim Wu wrote:


My apologies if it is too obvious, but did you count the clock cycle
that sets up the read address as one of the TWO clock cycles?

If you can post your code or waveform, that would be helpful.

Jim Wu
jimwu88NOOOOOSPAM@yahoo.com

io@duke.edu wrote in message news:<Pine.GSO.4.56.0308051041170.29999@hudson11.acpub.duke.edu>...

Hi -

I am trying to run a very simple simulation to verify the functionality of
the "block ram" component in my spartan ii fpga. I am using modelsim
tools that I downloaded from the xilinx website, and I'm using the
"ramb4_s8" primitive. The simulation appears to work properly except that
there appears to be a delay of one clock cycle when reading from the
memory. In other words, if I enable the ram, deassert the write enable,
and select the read address, I need TWO rising clock edges to get the
correct data to appear at the data_out port. I am doing a simple
behavioral simulation so there shouldn't be any delay issues involved.
The data sheet clearly shows that I should only need one rising clock edge
to execute the read. Any ideas? Thanks very much!!!

--Iyad

-------------------------------
Iyad Obeid
Dept. of Biomedical Engineering
Duke University
io@duke.edu
(919)660-5104 www.duke.edu/~io


-------------------------------
Iyad Obeid
Dept. of Biomedical Engineering
Duke University
io@duke.edu
(919)660-5104 www.duke.edu/~io
Click to expand...
-------------------------------
Iyad Obeid
Dept. of Biomedical Engineering
Duke University
io@duke.edu
(919)660-5109 www.duke.edu/~io
 
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