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There's no direct equivalent; VHDL does not have Verilog'sHello
I am new to VHDL and would like to know how to model pmos and nmos in
VHDL. In verilog we use the keyword pmos and nmos. IS there an
equivalent in VHDL? Please provide an example
On 19 Jun 2006 10:51:50 -0700, krithiga81@yahoo.com wrote:
Hello
I am new to VHDL and would like to know how to model pmos and nmos in
VHDL. In verilog we use the keyword pmos and nmos. IS there an
equivalent in VHDL? Please provide an example
There's no direct equivalent; VHDL does not have Verilog's
switch-level primitives.
Verilog's pmos and nmos are actually easy enough to reproduce in
VHDL, because they are unidirectional. The real problems start
when you try to model bidirectional primitives (tran, tranif...);
this is really tough in VHDL, and gave rise to a flurry of academic
papers in the late 1980s. If you Google for "zero ohm link VHDL"
you will almost certainly find the models on Ben Cohen's
website, which are a lot better than nothing although they do
have certain limitations.
Finally, note that VHDL users commonly use std_(u)logic to model
digital signals; with only two possible driving strengths other than
hi-Z, this is somewhat less expressive than the nine strengths
you can use on Verilog nets. It's easy to make a VHDL data
type that roughly mimics the behaviour of Verilog drive strength
(apart from the capacitive hold magic) but of course it won't be
standard, and you will need to write conversion functions to map
it to and from std_logic.
Oh, the pmos and nmos models...
entity nmos is
port (
p_Out : out std_logic;
p_In : in std_logic;
p_Gate: in std_logic
);
end;
architecture Simple of nmos is
begin
process(p_In, p_Gate)
variable control: std_Logic;
begin
case p_Gate is
when '0' | 'L' => p_Out <= 'Z';
when '1' | 'H' => p_Out <= p_In;
when others => p_Out <= 'X';
end case;
end process;
end;
rnmos can be modelled by using a "weakening" function on the
input, so that '1' and '0' on the input are mapped to 'H' and 'L'
respectively.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
May I ask why do you need it?I am new to VHDL and would like to know how to model pmos and nmos in
VHDL.
krithiga81@yahoo.com wrote:
I am new to VHDL and would like to know how to model pmos and nmos in
VHDL.
May I ask why do you need it?
Ralf
I know, that Verilog offers a lot of these low-level circuit components,The rpmos is modeled in Verilog as
this is part of a Verilog model
rpmos (P_P, su1, PU_SIG); //
and this needs to be modeled in VHDL as we create Verilog and VHDL
models