V
Verictor
Guest
Hi,
I have a group of design files are in *.v format. The top level test
environment files, however, are in *.sv (SystemVerilog) format.
Simulator is Ncverilog. All files have passed Ncverilog individually
(no syntax errors etc). But when simulating the whole system, ie.,
*.sv + *.v, one problem happened. Some *.v files contain keywords used
in SystemVerilog. For example, one *.v file has variable call "final",
which is not a keyword in Verilog but *is* in SystemVerilog. Those *.v
files are not supposed to be edited due to IP issues. It will be
clumpsy to change so many variable names too.
The simulation option for ncverilog I used is +sv (ignore others
irrelevent to this topics). Are there ways in ncverilog to specify
which option is for *.v and the other for *.sv?
Thanks.
I have a group of design files are in *.v format. The top level test
environment files, however, are in *.sv (SystemVerilog) format.
Simulator is Ncverilog. All files have passed Ncverilog individually
(no syntax errors etc). But when simulating the whole system, ie.,
*.sv + *.v, one problem happened. Some *.v files contain keywords used
in SystemVerilog. For example, one *.v file has variable call "final",
which is not a keyword in Verilog but *is* in SystemVerilog. Those *.v
files are not supposed to be edited due to IP issues. It will be
clumpsy to change so many variable names too.
The simulation option for ncverilog I used is +sv (ignore others
irrelevent to this topics). Are there ways in ncverilog to specify
which option is for *.v and the other for *.sv?
Thanks.