Mixing simulation of behavioral and synthesized code

[Silvano Bettinzana]

Dear friends,

I'm a novice and playing with Xilinx ISE Webpack and ModelsimXE.
I have a 'TOP' Verilog module in which I have instanced 2 module: 'A' and
'B';
I have a testbench for 'TOP' and want to simulate with 'A' sinthesized and
'B' not synthesized ('B' is not synthesizable; it has for example '#...'
statement).
Is this possible ?
How ?

Thanks and Regards

Silvano

 

[pl[N0SP4M]apri]

Silvano Bettinzana wrote:

Dear friends,

I'm a novice and playing with Xilinx ISE Webpack and ModelsimXE.
I have a 'TOP' Verilog module in which I have instanced 2 module: 'A' and
'B';
I have a testbench for 'TOP' and want to simulate with 'A' sinthesized and
'B' not synthesized ('B' is not synthesizable; it has for example '#...'
statement).
Is this possible ?

I believe so, unless this isn't implemented in WebPack...

How ?

You can ask ISE to generate a VHDL/Verilog simulation model at most
stages of implementation, i.e. post-translate, post-map, post-p&r. All
you need to do is take the generated file and use it instead of your
original source code. I don't know for Verilog, but the VHDL model has
exactly the same entity declaration, except the GENERICs have been
hard-coded, so the same testbenches can be used in each sim with only
very minor modifications... The only annoyance I've had is that your
signal names tend to be flattened out, and I'm not aware of any signal
name equivalence file. Hope this helps,

--
Pierre-Olivier

-- to email me directly, remove all [N0SP4M] from my address --