Mixed VHDL and Verilog question

Hello everyone.

Would someone please provide an answer to the following "simple"
question?

How do you override the default value of the parameters of a Verilog
module when you instantiate such a module in a VHDL top-level entity
or testbench?

Would the use of "generic map" work?

Thank you.
Marco

 

[Mike Treseler]

marcoa.castellon@gmail.com wrote:

How do you override the default value of the parameters of a Verilog
module when you instantiate such a module in a VHDL top-level entity
or testbench?

With a text editor.

Would the use of "generic map" work?

I can't imagine how.

-- Mike Treseler

 

[Dwayne Dilbeck]

Would someone please provide an answer to the following "simple"
question?
Simple question -> complex ansewer.

Would the use of "generic map" work?
It will depend on the tools. All of the EDA SW I test, will correctly pass

a vhdl generic mapping to a verilog parameter. If it doesn't the tool has
a bug. Some tools will even support generaic maping inside of a
configuration statement to overide verilog parameters. My best advice is
try it with your software. If it doesn't work file a bug. They may come
back and give you a work around.