mixed Verilog/VHDL design

B

botao

Guest
Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB, and
the Verilog one into VERILOG_LIB, then I am planning to code up a top level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

thanks,

---Lee
 
"botao" <blee@qualcomm.com> writes:

Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB, and
the Verilog one into VERILOG_LIB, then I am planning to code up a top level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.
Click to expand...
AFAIK, you loose. Verilog has no understanding of Libraries, so it's a
plain no-go.


--Kai
 
anybody hate verilog :)

"botao" <blee@qualcomm.com> wrote in message
news:cch8gu$n8v$1@fair.qualcomm.com...
Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB, and
the Verilog one into VERILOG_LIB, then I am planning to code up a top
level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

thanks,

---Lee
Click to expand...
 
On Wed, 07 Jul 2004 20:14:47 GMT, Kai Harrekilde-Petersen
<khp@harrekilde.dk> wrote:

"botao" <blee@qualcomm.com> writes:
[...]
comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

AFAIK, you loose. Verilog has no understanding of Libraries, so it's a
plain no-go.
Click to expand...
Not entirely true. Find out about the `uselib directive (not
all tools support it). Then there's the Verilog-2001 library and
configuration mechanism; again, tool support is variable, and
some aspects of the standard are left for tool vendors to
define anyway.

The basic problem is that a library in Verilog, whether implemented
through `uselib or V2k1 library/configuration, is a collection of
source files, whereas a VHDL library is a collection of compiled
design units. Mixed-language tools have the unenviable task
of making these two things interoperate sensibly.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
In fact you can mix the both components, but perhaps no so simple taht
expected.

You can instanciate the both component into the same top level file, if
the top is a vhdl model, you need define the formal component prototype
into a package, or into the architecture_declarative_part.

After this is a problem of instantiation.

Do a compilation/synthesis (as verilog netlist) of your vhdl part, do
the same with the verilog file; and now you have no more problem to mix
them.

If you only want do simulation. You can use Modelsim, that offer you
capability to mix the both code.

During instantiation (from the verilog point of view), you use the
first found model of the component that you have into the defined
working library.
The problem is that lot of tools haven't the same 'structure' to handle
vhdl and verilog model; and the 'structures' aren't easilly mixable.
But if you can esthablish a same format netlist for the both component,
generally you can mix them easilly.

JaI


botao wrote:

Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB, and
the Verilog one into VERILOG_LIB, then I am planning to code up a top level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

thanks,

---Lee
Click to expand...
 
On Wed, 7 Jul 2004 16:52:18 -0700, "botao" <blee@qualcomm.com> wrote:

anybody hate verilog :)
Click to expand...
Janick Bergeron memorably wrote that he uses both VHDL and
Verilog, and at any given time he prefers whichever he's
not using at that time. I reckon that's not a bad summary.

Of course, when we have SystemVerilog 3.1a, which includes
everything that you could possibly want from VHDL, C++, PSL,
Vera, e and just about every other language you've ever
thought of, then we can use SystemVerilog for everything.
Presumably that means we will be able to dislike it
all the time.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Just an Illusion wrote:

Hi Swapnajit,

Swapnajit Mittra wrote:

"botao" <blee@qualcomm.com> wrote in message
news:<cch877$n40$1@fair.qualcomm.com>...


Have a tough problem ...

I need to compare 2 components with the same interface, one
component is
implemented in VHDL, the other is in Verilog.

snip

---Lee



If you have a logic equivalency checker (Verplex Tuxedo, Cadence
Chrysalis etc.), read in both the modules and do an equivalency
check. This is the *only* practical way to make sure they are 100%
equivalent for two real life designs.

You are right, but only if the both model have the same number of
register (ff and d-latch).
But that not solve the Botao problem, if the tool can't handle the
mixed types at same time.
More you need have 'compatible' levels of file, if the vhdl is a
behavioral description, you can have lot of problems to compare it
with a gate level once.
Event if is it theoricaly possible.

Otherwise, you need use other formal tool (not equivalent checker).
With formal tool, you can create a wrapper, which instanciate the both
components (and you have an other time the same problem), where
equivalent outputs are connected by an xor (resp. xnor) function and
connected to the outputs of the wrapper; you can merged all the xor
(resp. xnor) output throught a or (resp. and) function to give only
one output.
After you just need check that output(s) is(are) always 0 (resp. 1).

By this way you can have 100% equivalence proof, independently of
register number.


- Swapnajit. --
Project VeriPage::: http://www.project-veripage.com



JaI
Click to expand...
 
Jonathan Bromley <jonathan.bromley@doulos.com> writes:
Of course, when we have SystemVerilog 3.1a, which includes
everything that you could possibly want from VHDL, C++, PSL,
Vera, e and just about every other language you've ever
thought of, then we can use SystemVerilog for everything.
Presumably that means we will be able to dislike it
all the time.
Click to expand...
So SystemVerilog is the PL/I of HDLs?
 
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