mixed Verilog/VHDL design

B

botao

Guest
Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB, and
the Verilog one into VERILOG_LIB, then I am planning to code up a top level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

thanks,

---Lee
 
"botao" <blee@qualcomm.com> wrote in message news:<cch877$n40$1@fair.qualcomm.com>...
Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB, and
the Verilog one into VERILOG_LIB, then I am planning to code up a top level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

thanks,

---Lee
I believe that if you use Verilog 2001 configurations, ModelSim
supports referencing components from both Verilog and VHDL libraries.
 
I believe that if you use Verilog 2001 configurations, ModelSim
supports referencing components from both Verilog and VHDL libraries.
As far as you do not use OEM versions of Modelsim ... isn't it?
 
Hi Swapnajit,

Swapnajit Mittra wrote:

"botao" <blee@qualcomm.com> wrote in message news:<cch877$n40$1@fair.qualcomm.com>...


Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.


snip

---Lee



If you have a logic equivalency checker (Verplex Tuxedo, Cadence
Chrysalis etc.), read in both the modules and do an equivalency
check. This is the *only* practical way to make sure they are
100% equivalent for two real life designs.


You are right, but only if the both model have the same number of
register (ff and d-latch).
But that not solve the Botao problem, if the tool can't handle the mixed
types at same time.
More you need have 'compatible' levels of file, if the vhdl is a
behavioral description, you can have lot of problems to compare it with
a gate level once.
Event if is it theoricaly possible.

Otherwise, you need use other formal tool (not equivalent checker).
With formal tool, you can create a wrapper, which instanciate the both
components (and you have an other time the same problem), where
equivalent outputs are connected by an xor (resp. xnor) function and
connected to the outputs of the wrapper; you can merged all the xor
(resp. xnor) output throught a or (resp. and) function to give only one
output.
After you just need check that output(s) is(are) always 0 (resp. 1).

By this way you can have 100% equivalence proof, independently of
register number.


- Swapnajit.
--
Project VeriPage::: http://www.project-veripage.com
JaI
 
Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB,
and
the Verilog one into VERILOG_LIB, then I am planning to code up a top
level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in
VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

thanks,

---Lee

If you have a logic equivalency checker (Verplex Tuxedo, Cadence
Chrysalis etc.), read in both the modules and do an equivalency
check. This is the *only* practical way to make sure they are
100% equivalent for two real life designs.

- Swapnajit.
--
I am using the code as an test case. The actual components are quite
complicated, and I donot exactly how they are actually designed.

---Lee
 

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