mixed Verilog/VHDL design

[botao]

Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB, and
the Verilog one into VERILOG_LIB, then I am planning to code up a top level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

thanks,

---Lee

 

[botao]

Have a tough problem ...

I need to compare 2 components with the same interface, one component is
implemented in VHDL, the other is in Verilog.
I compiled (using modelsim if it matters) the VHDL one into VHDL_LIB,
and
the Verilog one into VERILOG_LIB, then I am planning to code up a top
level
testbench in Verilog, something like

comp u_vhdl (clk, ...); // want to use the comp in VHDL_LIB
comp u_verilog (clk, ...); // want to use the comp in
VERILOG_LIB


how do I exactly do this in Verilog? I know in VHDL one can do this as

u_vhdl: ENTITY VHDL_LIB.comp ...

but I have to use Verilog this time.

thanks,

---Lee

If you have a logic equivalency checker (Verplex Tuxedo, Cadence
Chrysalis etc.), read in both the modules and do an equivalency
check. This is the *only* practical way to make sure they are
100% equivalent for two real life designs.

- Swapnajit.
--

I am using the code as an test case. The actual components are quite
complicated, and I donot exactly how they are actually designed.

---Lee

 

[botao]

"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0407080623.57e0d6b1@posting.google.com...

I believe that if you use Verilog 2001 configurations, ModelSim
supports referencing components from both Verilog and VHDL libraries.

As far as you do not use OEM versions of Modelsim ... isn't it?

I do have the full featured version ... Not using Verilog 2001 yet, can you
guys poing me to any webpage which explains the configuration thing?

---Lee