Mixed Simulation of Design (VHDL and Verilog)

[Mirza.AR]

Dear all,

I need to simulate my design with a design whihc was done already in
verilog. Design in Verilog will communicate with the Design in VHDL.

I did simulation of my Design in VHDL using a test bench, but for
practical reasons I need to used the other design in same test.

[b:67228fc63e]HOW TO USE A DESIGN(VERILOG) IN A VHDL DESIGN SIMULATION??

PLEASE ADVISE, ANY TIPS, ANY KIND OF LITRATURE??[/b:67228fc63e]

thanks in advance,

mirza

 

On Jul 12, 1:10 am, "Mirza.AR" <mirza.at...@gmail.com> wrote:

Dear all,

I need to simulate my design with a design whihc was done already in
verilog. Design in Verilog will communicate with the Design in VHDL.

I did simulation of my Design in VHDL using a test bench, but for
practical reasons I need to used the other design in same test.

[b:942b7964ee]HOW TO USE A DESIGN(VERILOG) IN A VHDL DESIGN SIMULATION??

PLEASE ADVISE, ANY TIPS, ANY KIND OF LITRATURE??[/b:942b7964ee]

thanks in advance,

mirza

Just about every simulator made in the last couple of years supports
mixed language design.

The only exceptions would be the free ones; CVER, Icarus, GHDL, etc.

Just be sure to use explicit (named) port connections.

G.