Mixed signal verification using verilog and spice ?

[ric]

Hi guys,I am now doing custom IC design and face a problem of how to
verify it...
My design is a digital block(a filter using a lot of alike taps) in
the project but uses custom cells to reduce area. The design is too
large(500k using .13 technology) to use Spice to simulate ,and can't
use back-annotation on verilog netlist(we don't have a cell library
-_-! ). One method I could find out is to use TimeMill to simulate :
1.extract spice file from layout gds(one of the tap,small enough
to run simulation)
2.use original verilog netlist(pre-layout)
3.add them together using Timemill(and test vectors corresponds to
verilog netlist, no vectors dirrectly add to the spice netlist)
But the question is I am not familiar with Timemill and I could not
find any information about how to merge verilog and spice together...
Any help will be appreciated!

 

[jools]

If you've developed custom cells for the verilog aspect just write some
models for your gates and include in the form of a library. This is all the
foundry who supply standard cells do. Their standard cells have a module in
a library which describes a cells behaviour. This library is included when
you perfrom a simulation. Look at an example library for hhow to structure
it or read the cadence/synopsys docs.

"ric" <ric_ma@attansic.com.tw> wrote in message
news:e56276c6.0402222329.734184d3@posting.google.com...

Hi guys,I am now doing custom IC design and face a problem of how to
verify it...
My design is a digital block(a filter using a lot of alike taps) in
the project but uses custom cells to reduce area. The design is too
large(500k using .13 technology) to use Spice to simulate ,and can't
use back-annotation on verilog netlist(we don't have a cell library
-_-! ). One method I could find out is to use TimeMill to simulate :
1.extract spice file from layout gds(one of the tap,small enough
to run simulation)
2.use original verilog netlist(pre-layout)
3.add them together using Timemill(and test vectors corresponds to
verilog netlist, no vectors dirrectly add to the spice netlist)
But the question is I am not familiar with Timemill and I could not
find any information about how to merge verilog and spice together...
Any help will be appreciated!

 

[ric]

Yes,you are right,during my RTL simulation,I do use a user-defined
library.But there is no fanout or WLM infomation in it.My purpose is
to verify if the layout works.
After a few days searching in the newsgroups and EPIC's
tutorials,now I find a solution:
1.Use Calibre to do RC extractions(in several
perspective:cell,sub-module,top-module).The extraction uses lumped-C
model for time saving.
2.Use Timemill/Powrmill to do the simulation.The top module could be
spice file or RTL netlist,the lower module can be spice cells
extracted from Calibre.The test vectors can be extracted from
previouslly generated dump file(.VCD).
Actually this method I think is like handle analog circuit except
using Timemill/Powrmill(capable and high speed for large digital
circuit).

Ric Ma
Attansic Inc.

"jools" <jmspam200@yahoo.com> wrote in message news:<c1humq$f7$1@ucsnew1.ncl.ac.uk>...

If you've developed custom cells for the verilog aspect just write some
models for your gates and include in the form of a library. This is all the
foundry who supply standard cells do. Their standard cells have a module in
a library which describes a cells behaviour. This library is included when
you perfrom a simulation. Look at an example library for hhow to structure
it or read the cadence/synopsys docs.

"ric" <ric_ma@attansic.com.tw> wrote in message
news:e56276c6.0402222329.734184d3@posting.google.com...
Hi guys,I am now doing custom IC design and face a problem of how to
verify it...
My design is a digital block(a filter using a lot of alike taps) in
the project but uses custom cells to reduce area. The design is too
large(500k using .13 technology) to use Spice to simulate ,and can't
use back-annotation on verilog netlist(we don't have a cell library
-_-! ). One method I could find out is to use TimeMill to simulate :
1.extract spice file from layout gds(one of the tap,small enough
to run simulation)
2.use original verilog netlist(pre-layout)
3.add them together using Timemill(and test vectors corresponds to
verilog netlist, no vectors dirrectly add to the spice netlist)
But the question is I am not familiar with Timemill and I could not
find any information about how to merge verilog and spice together...
Any help will be appreciated!

 

[jools]

Why not simply write a digital model for you cells, then back annotate. The
digital model is like the one in the library you use for standard cells.
Thinking I suppose you wont have a *.tlf file for your custom cells either,
this could be created unsing cadence' pearl tool though or synopsys'
equivalent product.

"ric" <ric_ma@attansic.com.tw> wrote in message
news:e56276c6.0402252050.2be0aa71@posting.google.com...

Yes,you are right,during my RTL simulation,I do use a user-defined
library.But there is no fanout or WLM infomation in it.My purpose is
to verify if the layout works.
After a few days searching in the newsgroups and EPIC's
tutorials,now I find a solution:
1.Use Calibre to do RC extractions(in several
perspective:cell,sub-module,top-module).The extraction uses lumped-C
model for time saving.
2.Use Timemill/Powrmill to do the simulation.The top module could be
spice file or RTL netlist,the lower module can be spice cells
extracted from Calibre.The test vectors can be extracted from
previouslly generated dump file(.VCD).
Actually this method I think is like handle analog circuit except
using Timemill/Powrmill(capable and high speed for large digital
circuit).

Ric Ma
Attansic Inc.

"jools" <jmspam200@yahoo.com> wrote in message
news:<c1humq$f7$1@ucsnew1.ncl.ac.uk>...
If you've developed custom cells for the verilog aspect just write some
models for your gates and include in the form of a library. This is all
the
foundry who supply standard cells do. Their standard cells have a module
in
a library which describes a cells behaviour. This library is included
when
you perfrom a simulation. Look at an example library for hhow to
structure
it or read the cadence/synopsys docs.

"ric" <ric_ma@attansic.com.tw> wrote in message
news:e56276c6.0402222329.734184d3@posting.google.com...
Hi guys,I am now doing custom IC design and face a problem of how to
verify it...
My design is a digital block(a filter using a lot of alike taps) in
the project but uses custom cells to reduce area. The design is too
large(500k using .13 technology) to use Spice to simulate ,and can't
use back-annotation on verilog netlist(we don't have a cell library
-_-! ). One method I could find out is to use TimeMill to simulate :
1.extract spice file from layout gds(one of the tap,small enough
to run simulation)
2.use original verilog netlist(pre-layout)
3.add them together using Timemill(and test vectors corresponds to
verilog netlist, no vectors dirrectly add to the spice netlist)
But the question is I am not familiar with Timemill and I could not
find any information about how to merge verilog and spice together...
Any help will be appreciated!

 

[ric]

One of the problems is I can not run back-annotation because the SDF
extracted
from layout gds is annotated on the transistors,not the gate.
What is the use of .tlf file?
Our project is very timing critical,and we can not aford to build a
library for frontend(I am the frontend,unfortunately),we only have
cell layout and chip layout based on it.
Now I find running simulation using this analog method is really
painful...

"jools" <jmspam200@yahoo.com> wrote in message news:<c1kmhp$715$1@ucsnew1.ncl.ac.uk>...

Why not simply write a digital model for you cells, then back annotate. The
digital model is like the one in the library you use for standard cells.
Thinking I suppose you wont have a *.tlf file for your custom cells either,
this could be created unsing cadence' pearl tool though or synopsys'
equivalent product.

 

[jools]

a *.tlf file is the timing library format, it contains information on how a
gate behaviours in terms of switching etc. You can also generate them for
transistors too, i think. Read up on 'pearl' all you need is in there.

If you design is timing critical you want to use what ive suggested.

"ric" <ric_ma@attansic.com.tw> wrote in message
news:e56276c6.0402271901.fa5edc3@posting.google.com...

One of the problems is I can not run back-annotation because the SDF
extracted
from layout gds is annotated on the transistors,not the gate.
What is the use of .tlf file?
Our project is very timing critical,and we can not aford to build a
library for frontend(I am the frontend,unfortunately),we only have
cell layout and chip layout based on it.
Now I find running simulation using this analog method is really
painful...

"jools" <jmspam200@yahoo.com> wrote in message
news:<c1kmhp$715$1@ucsnew1.ncl.ac.uk>...
Why not simply write a digital model for you cells, then back annotate.
The
digital model is like the one in the library you use for standard cells.
Thinking I suppose you wont have a *.tlf file for your custom cells
either,
this could be created unsing cadence' pearl tool though or synopsys'
equivalent product.