T
Tanuj Aggarwal
Guest
Hi,
I have been tring to do mixed signal simulations in cadence for
a low power PLL. the supply voltage for the PLL is around 250mV. I
have a DCO followed by a verilog code for a synchronous down counter.
Bascially I want to divide the DCO clock by a factor of 64 generate
two clocks of frequency dco/8 and dco/64.
I specified the interface element property by selecting each instant
Mixed-Signal->Interface Elemnts -> Instance and set the a2d properties
as
a2d_tx 1n
a2d_v0 0.1
a2dv1 0.15
and
d2a properties as
d2a_tr as 30p
d2a_tf as 30p
d2a_vh as 0.25
d2avl as 0
the frequencies did not get generated properly.
I have a few questions, I did not copy the MOs cell in the analogLib
library to my design library is that a problem, Also is it fine to
specify the d2a and a2d interface properties for each instance like
this, please suggest any prossible solutions to this problem
Regards
Tanuj
I have been tring to do mixed signal simulations in cadence for
a low power PLL. the supply voltage for the PLL is around 250mV. I
have a DCO followed by a verilog code for a synchronous down counter.
Bascially I want to divide the DCO clock by a factor of 64 generate
two clocks of frequency dco/8 and dco/64.
I specified the interface element property by selecting each instant
Mixed-Signal->Interface Elemnts -> Instance and set the a2d properties
as
a2d_tx 1n
a2d_v0 0.1
a2dv1 0.15
and
d2a properties as
d2a_tr as 30p
d2a_tf as 30p
d2a_vh as 0.25
d2avl as 0
the frequencies did not get generated properly.
I have a few questions, I did not copy the MOs cell in the analogLib
library to my design library is that a problem, Also is it fine to
specify the d2a and a2d interface properties for each instance like
this, please suggest any prossible solutions to this problem
Regards
Tanuj