Mixed Signal IC design-flow

[Thomas Ussmueller]

Hello everybody,

I am currently designing a fractional-n PLL in Cadence. The problem is
that up to now I only have experience in analog IC design. But for the
PLL I need some digital parts. I'd like to generate the layout of these
automatically by a place and route tool.

Which tools do I need to synthesize, place and route the digital design
(VHDL code) and then include it in my analog layout? What would the
design flow look like?

Thanks for your help
Thomas

 

[leanderdeng@gmail.com]

Hi Thomas,

It largely depends on your case. Based on my knowledge, for the digital
part, you can use Encounter RTL compiler to synthesize and first
Encounter to place&route. You can invoke your analog part in the Place
and Route tools.

You also need to consider how to simulate and verify your design. With
Fast SPICE tools such as UltraSim and NanoSim, you can verify the
analog netlist plus digital gate level netlist, even with post-layout
RC. If the case is too large, the mixed signal simulation is need,
which combines the SPICE tools and digital verification tools.

In a word, there is no flow for all the mixed-signal designs.

Yuchun

Thomas Ussmueller wrote:

Hello everybody,

I am currently designing a fractional-n PLL in Cadence. The problem is
that up to now I only have experience in analog IC design. But for the
PLL I need some digital parts. I'd like to generate the layout of these
automatically by a place and route tool.

Which tools do I need to synthesize, place and route the digital design
(VHDL code) and then include it in my analog layout? What would the
design flow look like?

Thanks for your help
Thomas

 

[John Gianni]

Talk to your local Cadence sales team who can show you a three-part AMS
Methodogy "kit" containing a complete 10/100 Ethernet Phy design (with
multiple PLLs) built completely in the Cadence 90nm generic process
using the 500-cell Cadence standard cell library and 100% Cadence tools
& methodologies.

Basically, there are three methodology sections that walk you through:
- Top-level AMS simulation strategies and methodologies, including
parasitics
- Block authoring methodologies including analog synthesis & IP reuse
- Virtuoso digital implementation including mixed floorplanning, area
estimation, place & route, and mixed-signal integration, all within the
Virtuoso environment

All three of these well-honed methodologies are fully explained in the
kit methodology documentation available at http://downloads.cadence.com
for those with valid licenses for these kits. It's not just talk. Every
single step is performed, down to the last parastic of the last
transistor.

In summary, all that you want already exists; just ask your local sales
team for assistance.

Hope this helps ... Good luck,
John Gianni
--
Nothing I say here is prior reviewed nor sanctioned by my employer!

 

[John Gianni]

All three of these well-honed methodologies are fully explained in the
kit methodology documentation available at http://downloads.cadence.com

I just realized I didn't provide the complete link to the AMS & RF
methodology kits.

1. Go to http://downloads.cadence.com

2. Press on the "Linux" tab.

3. Select the "AMSKIT51" or "RFKIT52" links.

If you have the proper licence (obtained from your local Cadence sales
contact), you can immediately begin using the methodologies, IP, and
services inherent in those complete methodology kits to design complex
AMS & RF chips.

Each download contains a complete design, a complete design kit
(containing everything in the custom and digital side necessary to
design the targeted chip), and complete documentation showing the
methodology from start to finish that is documented and supported and
tested to work, release after release; and which is improved over time
with all new releases and methodologies.

As always, so all benefit,
John Gianni
--
Everything I say here is a personal opinion not prior sanctioned by my
employer!