Mixed language

[jjsandoval1962@aol.com]

Hi,

I have a VHDL design and I want to verify the design with a verilog
test-bench. I have heard that ModelSim Plus (tools runs on a single
kernel for both languages) allows you do this. Is anyone out there
already doing this? Do you need any wrappers?

Is it as simple as this:

module testbench;

reg sysClk;

// clock generation
initial
begin
sysClk = 0;
forever # (`sysClkPeriod/2) sysClk <= !sysClk;
end

// VHDL design instantiation
u_VHDL u_VHDL (
.clk (clk),
.reset (reset),
.in1 (in1),
.in2 (in2),

.out1 (out1),
.out2 (out2),
.out3 (out3)
);

endmodule:testbench

 

[Ajeetha]

This should work in most of the tools, I've done it myself in NC, VCS
and MTI.

Ajeetha
www.noveldv.com

 

hi,
yes it does work. You can use verilog test benches for VHDL design
files. But the problem comes if u are using Verilog PLI's for VHDL
design files. In that case the handles to modules are not able to
recognize VHDL entities.
If anyone has successfully done this please let me know because I
was getting error when I was doing that. Thank You

Best Regards,