Mixed language simulation on the cheap

R

Rob Gaddi

Guest
I only speak VHDL. Unfortunately, the memory interface generator in
ISE 11.2 for Spartan-6 only speaks Verilog. Specifically, the device
models underneath are in the silly encrypted Verilog format, so I can't
even go spelunking around.

So far, Modelsim XE Starter (free) has been sufficient for all my
simulation needs. In order to do mixed language simulation, however,
I'd need to step up to Modelsim PE, which I just had quoted to me for
slightly under $10K for a one year license.

All I really need it for is to simulate out my memory interface stuff;
I have very little interest in adding lots of mixed language
programming to my world. And so ten kilobucks is really quite the
chunk of change for solving one problem.

Does anyone know of any better solutions for mixed language
simulation? I had been thinking this would cost me somewhere in the
$2K ballpark; at $10K I'd be better off sticking with "program and
pray".

--
Rob Gaddi, Highland Technology
Email address is currently out of order
 
Rob Gaddi wrote:

Does anyone know of any better solutions for mixed language
simulation? I had been thinking this would cost me somewhere in the
$2K ballpark; at $10K I'd be better off sticking with "program and
pray".
Click to expand...
Or infer the block ram from vhdl code.

-- Mike Treseler
 
On Thu, 13 Aug 2009 15:24:19 -0700
Mike Treseler <mtreseler@gmail.com> wrote:

Rob Gaddi wrote:

Does anyone know of any better solutions for mixed language
simulation? I had been thinking this would cost me somewhere in the
$2K ballpark; at $10K I'd be better off sticking with "program and
pray".

Or infer the block ram from vhdl code.

-- Mike Treseler
Click to expand...
Not block RAM. Giant complex multiple FIFO interface to external DDR2.

--
Rob Gaddi, Highland Technology
Email address is currently out of order
 
Rob Gaddi schrieb:
I only speak VHDL. Unfortunately, the memory interface generator in
ISE 11.2 for Spartan-6 only speaks Verilog. Specifically, the device
models underneath are in the silly encrypted Verilog format, so I can't
even go spelunking around.

So far, Modelsim XE Starter (free) has been sufficient for all my
simulation needs. In order to do mixed language simulation, however,
I'd need to step up to Modelsim PE, which I just had quoted to me for
slightly under $10K for a one year license.

All I really need it for is to simulate out my memory interface stuff;
I have very little interest in adding lots of mixed language
programming to my world. And so ten kilobucks is really quite the
chunk of change for solving one problem.

Does anyone know of any better solutions for mixed language
simulation? I had been thinking this would cost me somewhere in the
$2K ballpark; at $10K I'd be better off sticking with "program and
pray".
Click to expand...
Aldec recently had an offer of their mixed-language windows simulator
ActiveHDL for around $1,600. As far as I remember though, that was per
year. So it might not be quite what you are looking for, assuming the
offer is even still available in the first place. It is largely script
compatible to modelsim.
 
On Aug 13, 4:03 pm, Rob Gaddi <rga...@technologyhighland.com> wrote:
I only speak VHDL.  Unfortunately, the memory interface generator in
ISE 11.2 for Spartan-6 only speaks Verilog.  Specifically, the device
models underneath are in the silly encrypted Verilog format, so I can't
even go spelunking around.

So far, Modelsim XE Starter (free) has been sufficient for all my
simulation needs.  In order to do mixed language simulation, however,
I'd need to step up to Modelsim PE, which I just had quoted to me for
slightly under $10K for a one year license.

All I really need it for is to simulate out my memory interface stuff;
I have very little interest in adding lots of mixed language
programming to my world.  And so ten kilobucks is really quite the
chunk of change for solving one problem.

Does anyone know of any better solutions for mixed language
simulation?  I had been thinking this would cost me somewhere in the
$2K ballpark; at $10K I'd be better off sticking with "program and
pray".

--
Rob Gaddi, Highland Technology
Email address is currently out of order
Click to expand...
Hello Rob,

The ISIM simulator that comes with ISE supports mixed VHDL and Verilog
simulation. It comes standard with all editions of ISE. Look here:
http://www.xilinx.com/tools/logic.htm, and click on the ISIM link for
details.

Regards,

John McCaskill
Faster Technology
Xilinx Authorized Training Provider
http://www.fastertechnology.com/training.html
 
On Thu, 13 Aug 2009 14:03:07 -0700, Rob Gaddi <rgaddi@technologyhighland.com>
wrote:

I only speak VHDL. Unfortunately, the memory interface generator in
ISE 11.2 for Spartan-6 only speaks Verilog. Specifically, the device
models underneath are in the silly encrypted Verilog format, so I can't
even go spelunking around.

So far, Modelsim XE Starter (free) has been sufficient for all my
simulation needs. In order to do mixed language simulation, however,
I'd need to step up to Modelsim PE, which I just had quoted to me for
slightly under $10K for a one year license.

All I really need it for is to simulate out my memory interface stuff;
I have very little interest in adding lots of mixed language
programming to my world. And so ten kilobucks is really quite the
chunk of change for solving one problem.

Does anyone know of any better solutions for mixed language
simulation? I had been thinking this would cost me somewhere in the
$2K ballpark; at $10K I'd be better off sticking with "program and
pray".
Click to expand...
In ISE10, ISIM sort of works, and can handle Verilog memory models with some
limitations. ISIM ought to work at least as well in ISE11, Xilinx appeared to be
paying a lot of attention to improving it.

The limitations are (in ISE10) (a) Verilog memories can only be instantiated at
the top level of the testbench, not in e.g. an entity representing a SODIMM.
(This can be worked around, but it gets extremely painful for bidirectional
signals). And (b) connecting >1 memory module to the data bus (even with
correctly wired chip selects) doesn't work. (This is painful because the timing
calibration only works on the higher addressed memories and your testbench
probably wants to address the lower addressed memories; you can't leave either
half unpopulated and populating both doesn't work)

If you can live with these limitations, ISIM may be worth a look. As a bonus,
it's also cross-platform; you're not tied to Windows.

Either or both of these limitations may have been fixed in ISE11, but I was left
with the distinct impression by the Webcase folks that ISE12 was more likely.


The lack of VHDL memory models isn't Xilinx's fault; they supply the formerly
excellent Micron models, and Micron seem to have stopped supplying VHDL models
witd the DDR1 generation of memory.

But if MIG has stopped producing VHDL memory cores, I regard that as a seriously
bad development. Say it isn't so...

- Brian
 
On Aug 13, 10:03 pm, Rob Gaddi <rga...@technologyhighland.com> wrote:
I only speak VHDL.  Unfortunately, the memory interface generator in
ISE 11.2 for Spartan-6 only speaks Verilog.  Specifically, the device
models underneath are in the silly encrypted Verilog format, so I can't
even go spelunking around.

So far, Modelsim XE Starter (free) has been sufficient for all my
simulation needs.  In order to do mixed language simulation, however,
I'd need to step up to Modelsim PE, which I just had quoted to me for
slightly under $10K for a one year license.

All I really need it for is to simulate out my memory interface stuff;
I have very little interest in adding lots of mixed language
programming to my world.  And so ten kilobucks is really quite the
chunk of change for solving one problem.

Does anyone know of any better solutions for mixed language
simulation?  I had been thinking this would cost me somewhere in the
$2K ballpark; at $10K I'd be better off sticking with "program and
pray".
Click to expand...


You can synthesize the design to a netlist then use netgen to get a
functional simulation model. They are not fast but do the job.

Cheers,
Andy.
 
"Rob Gaddi" <rgaddi@technologyhighland.com> wrote in message
news:20090813140307.000017fb@unknown...
I only speak VHDL. Unfortunately, the memory interface generator in
ISE 11.2 for Spartan-6 only speaks Verilog. Specifically, the device
models underneath are in the silly encrypted Verilog format, so I can't
even go spelunking around.
Click to expand...
I assume they use SecureIP in which case you need a "new" Swift interface
license. This is a lot cheaper than a PE VHDL+Verilog license.

Hans
www.ht-lab.com


So far, Modelsim XE Starter (free) has been sufficient for all my
simulation needs. In order to do mixed language simulation, however,
I'd need to step up to Modelsim PE, which I just had quoted to me for
slightly under $10K for a one year license.

All I really need it for is to simulate out my memory interface stuff;
I have very little interest in adding lots of mixed language
programming to my world. And so ten kilobucks is really quite the
chunk of change for solving one problem.

Does anyone know of any better solutions for mixed language
simulation? I had been thinking this would cost me somewhere in the
$2K ballpark; at $10K I'd be better off sticking with "program and
pray".

--
Rob Gaddi, Highland Technology
Email address is currently out of order
Click to expand...
 
Rob Gaddi wrote:
I only speak VHDL. Unfortunately, the memory interface generator in
ISE 11.2 for Spartan-6 only speaks Verilog. Specifically, the device
models underneath are in the silly encrypted Verilog format, so I can't
even go spelunking around.

So far, Modelsim XE Starter (free) has been sufficient for all my
simulation needs. In order to do mixed language simulation, however,
I'd need to step up to Modelsim PE, which I just had quoted to me for
slightly under $10K for a one year license.

All I really need it for is to simulate out my memory interface stuff;
I have very little interest in adding lots of mixed language
programming to my world. And so ten kilobucks is really quite the
chunk of change for solving one problem.

Does anyone know of any better solutions for mixed language
simulation? I had been thinking this would cost me somewhere in the
$2K ballpark; at $10K I'd be better off sticking with "program and
pray".
Click to expand...
Does this help?

http://www.xilinx.com/support/answers/33118.htm

regards
Alan
--
Alan Fitch
Doulos
 
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