Mixed language simulation in VCS

[K.Hemanth]

HI All,
Can any one tell me how can I do the mixed language simulation using
VCS ?
If I have a some design in vhdl(verilog) code and testbench in
verilog(vhld) then how can I simulate such codes in VCS -MX ?

Please give me the step that are required to do the above mentioned
task.
If possible then please give the script for it.

Regards,
K.Hemantha.

 

Perhaps step one might be to read the manual?

Another resource is here: http://www.synopsys.com/support/support.html

 

[Ajeetha]

1. vhdlan dut.vhdl
2. vcs tb.v -mhdl
3. simv

Contatc vcs_support@synopsys.com for more! Or better read their manual.


You can also optinally write to me via email, though response time is
not guaranteed

Ajeetha, CVC
www.noveldv.com

K.Hemanth wrote:

HI All,
Can any one tell me how can I do the mixed language simulation using
VCS ?
If I have a some design in vhdl(verilog) code and testbench in
verilog(vhld) then how can I simulate such codes in VCS -MX ?

Please give me the step that are required to do the above mentioned
task.
If possible then please give the script for it.

Regards,
K.Hemantha.