Mixed language delta delay problem..

[uj101]

I'm facing a delta delay issue (CLK arriving before the data) for the
mixed language (VHDL/Verilog) simulation in modeltech. Has anyone
faced the same and knows any simple workaround (instead of inserting
#1 or after).

Thx

uj101

 

[KJ]

On Jul 18, 10:42 am, uj101 <uj...@yahoo.com> wrote:

I'm facing a delta delay issue (CLK arriving before the data) for the
mixed language (VHDL/Verilog) simulation in modeltech. Has anyone
faced the same and knows any simple workaround (instead of inserting
#1 or after).

Go back to your notes from basic logic design #101...Clock arriving
before the data is the way it is supposed to be. The rising edge of a
clock *causes* the output of a flop (i.e. the data) to change.

Similarly, inputs to a flop are sampled *at* the rising edge, the fact
that the data changes later (even if it is only one simulation delta
delay later) is picked up on the *next* clock edge.

KJ

 

[Mike Treseler]

Torsten Landschoff wrote:

How about the inverse problem (data arriving before the clock because
the clock is forwarded using concurrent signal assignments)?

A clock does not belong in a signal assignment.

-- Mike Treseler

 

[Torsten Landschoff]

On 18 Jul., 17:37, KJ <kkjenni...@sbcglobal.net> wrote:

On Jul 18, 10:42 am, uj101 <uj...@yahoo.com> wrote:

I'm facing a delta delay issue (CLK arriving before the data) for the
mixed language (VHDL/Verilog) simulation in modeltech. Has anyone
faced the same and knows any simple workaround (instead of inserting
#1 or after).

Go back to your notes from basic logic design #101...Clock arriving
before the data is the way it is supposed to be.  The rising edge of a
clock *causes* the output of a flop (i.e. the data) to change.

How about the inverse problem (data arriving before the clock because
the clock is forwarded using concurrent signal assignments)?

Greetings, Torsten

 

[Torsten Landschoff]

On 28 Jul., 15:32, Mike Treseler <mtrese...@gmail.com> wrote:

Torsten Landschoff wrote:
How about the inverse problem (data arriving before the clock because
the clock is forwarded using concurrent signal assignments)?

A clock does not belong in a signal assignment.

  -- Mike Treseler

So how does one generate the clock signal in a VHDL testbench?

Greetings, Torsten

 

[Mike Treseler]

On 28 Jul., 15:32, Mike Treseler <mtrese...@gmail.com> wrote:
A clock does not belong in a signal assignment.

Make that,
A clock does not belong in a signal assignment in synthesis code.

Torsten Landschoff wrote:

So how does one generate the clock signal in a VHDL testbench?

I use a simulation process with wait statements, as below.
See http://mysite.verizon.net/miketreseler/test_uart.vhd
for details.

-- Mike Treseler


...
begin -- process tb_clk
clk_s <= '0';
if now < rst_time then
rst_s <= '1'; -- rst once with clk running
else
rst_s <= '0'; -- then low forever
end if;
if done_s then wait; end if; -- Stop clock
wait for clk_cy/2; -- clock low
clk_s <= '1';
fixed_stim; -- auxiliary output from process
wait for clk_cy/2; -- clock high
end process tb_clk;

 

[Mike Treseler]

Mike Treseler wrote:

On 28 Jul., 15:32, Mike Treseler <mtrese...@gmail.com> wrote:
A clock does not belong in a signal assignment.

Make that,
A clock does not belong in a signal assignment in synthesis code

... or on the right side of a signal assignment in simulation.

 

[Mike Treseler]

Mike Treseler wrote:

Mike Treseler wrote:
On 28 Jul., 15:32, Mike Treseler <mtrese...@gmail.com> wrote:
A clock does not belong in a signal assignment.
Make that,
A clock does not belong in a signal assignment in synthesis code

... or on the right side of a signal assignment in simulation.

OK, how about:

A clock only belongs in a signal assignment,
in a testbench clock generator process.

-- Mike Treseler

"I think, therefore I post, one more time."