missing else in if esle staement

[balaji286@gmail.com]

hi,
if i miss an else block in the if else statement what are its
effects on synthesizing this design.

 

[Andy Peters]

balaji286@gmail.com wrote:

hi,
if i miss an else block in the if else statement what are its
effects on synthesizing this design.

Depends on whether you're describing registered or combinatorial logic.

-a

 

[Jason Zheng]

Andy Peters wrote:

balaji286@gmail.com wrote:

hi,
if i miss an else block in the if else statement what are its
effects on synthesizing this design.


Depends on whether you're describing registered or combinatorial logic.

-a

Regardless of sequential or combinational logic, if you assign values to

a variable in an if statement without an else clause, it means that if
none of the stated clauses are true, the varaible should retain the same
value or state prior to the execution of the if statement.

In seqential logic, the synthesis tool can deal with this non-trivially.
However, in combinational block, since there is nothing there to hold
the value, the synthesis tool would have to generate a latch to hold the
value until next time the block is activated. Unless, of course, you
assign a value to the variable before or after the if clause within the
SAME block. Here's an example:

always @ (a)
begin
out = 1'b1;
if (a) out = 1'b0;
end

so if a is 0, x, or z, out will be 1.

 

[John_H]

<balaji286@gmail.com> wrote in message
news:1132286771.244700.282280@g14g2000cwa.googlegroups.com...> hi,

if i miss an else block in the if else statement what are its
effects on synthesizing this design.

I recently saw someone's code where there were multiple if statements
assigning a single variable. Since I'd always been taught to assign my
values in one statement, I wondered if it was even legal to have multiple if
statements with non-blocking operators. The Verilog expert teaching a
coworkers class suggested the multiple ifs *were* valid and that they would
be interpreted in sequence.

So, if this is 100% true, your simulation would have reversed precedence,
synthesizing the later if (/else if/else) branch at a higher priority than
the previous confusing the order of non-exclusive states. If you have
exclusive states, I would expect the synthesis to be the same.

if( a[1] ) myval <= 1'b1;
else if( a[0] ) myval <= 1'b0;

a[1:0] would produce myval results of 1, 1, 0, and previous_myval for values
of 3, 2, 1, and 0, respectively.

if( a[1] ) myval <= 1'b1;
if( a[0] ) myval <= 1'b0;

here, the results are 0, 1, 0, and previous_myval because the a[0] executes
here where it wouldn't before.

if( a[1] ) myval <= 1'b1;
else if( ~a[1] & a[0] ) myval <= 1'b0;

should be the same as

if( a[1] ) myval <= 1'b1;
if( ~a[1] & a[0] ) myval <= 1'b0;

because the states - the conditionals evaluated - are exclusive.

I haven't verified the performance is as-expected in various synthesizers
and simulators because I personally don't like to break up an assignment
into bits. It's just bad form, producing confusion like yours. What
*would* happen if.....
....else.

- John_H

 

[svtechie@gmail.com]

Well said John_H. Though there may be some schenario where one wants to
implement priority encoder, in which case either this coding style can
be used

if( a[1] ) myval <= 1'b1;
else if( a[0] ) myval <= 1'b0;

or this:

if( a[0] ) myval <= 1'b1;
if( a[1] ) myval <= 1'b0;

As John_H mentioned, second one is little confusing & creates trouble
for Coverage tools. Assuming that everything is covered in simulation
(functionally), only one if block is effective in second coding style,
resulting in coverage to be 50% (instead of 100%).

my 2 cents

- svtechie
www.svtechie.com

 

[Jason Zheng]

svtechie@gmail.com wrote:

Well said John_H. Though there may be some schenario where one wants to
implement priority encoder, in which case either this coding style can
be used

if( a[1] ) myval <= 1'b1;
else if( a[0] ) myval <= 1'b0;

or this:

if( a[0] ) myval <= 1'b1;
if( a[1] ) myval <= 1'b0;

Ok, I assume you mean:

if (a[0]) myval <= 1'b0;
if (a[1]) myval <= 1'b1;

Right?

~jz

 

[John_H]

Don't assume (see below)

"Jason Zheng" <xin.zheng@jpl.nasa.gov> wrote in message
news:dm23t0$q1d$1@nntp1.jpl.nasa.gov...

svtechie@gmail.com wrote:
Well said John_H. Though there may be some schenario where one wants to
implement priority encoder, in which case either this coding style can
be used

if( a[1] ) myval <= 1'b1;
else if( a[0] ) myval <= 1'b0;

or this:

if( a[0] ) myval <= 1'b1;
if( a[1] ) myval <= 1'b0;

Ok, I assume you mean:
if (a[0]) myval <= 1'b0;
if (a[1]) myval <= 1'b1;

Right?

~jz

As I tried to point out, without the else the second conditional takes
precedence over the first. Is the first condition met? Yes? But WAIT!
The second condition is valid, so I'll use that. It's the same as if the
2nd condition without the else were the first condition WITH the else.

Please... use the else. These confusions are so much easier to avoid.