MIPI M-PHY and FPGA?

[mnentwig]

Hi,

does anybody know whether it is possible (or impossible) to use an FPGA'
serial transceivers for a MIPI type 2 M-PHY link (i.e. 1.5 GBit/s)?
Xlinx' book http://www.xilinx.com/publications/archives/books/serialio.pd
makes it look easy, but I suspect this gets very difficult once moving awa
from an established standard.

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[Antti]

On Tuesday, 28 October 2014 12:18:33 UTC+1, mnentwig wrote:

Hi,

does anybody know whether it is possible (or impossible) to use an FPGA's
serial transceivers for a MIPI type 2 M-PHY link (i.e. 1.5 GBit/s)?
Xlinx' book http://www.xilinx.com/publications/archives/books/serialio.pdf
makes it look easy, but I suspect this gets very difficult once moving away
from an established standard.

---------------------------------------
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M-PHY is not supported

 

[Antti]

On Friday, 19 December 2014 10:23:47 UTC+1, mnentwig wrote:

I've heard the same, that the low-rate mode is one problem. Don't think you
can bring up the interface in HSx mode in a standardized way
(product-specific "hacks" via some 3-wire interface etc could still work).
I wonder whether one could reconfigured the line drivers "on-the-fly" and
drive the low speed mode from the FPGA fabric, bypassing the SERDES etc
hardware blocks.

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the low-speed can be patched in if desired.
for some reason I did think there are more complications ..

 

[mnentwig]

I've heard the same, that the low-rate mode is one problem. Don't think yo
can bring up the interface in HSx mode in a standardized wa
(product-specific "hacks" via some 3-wire interface etc could still work).
I wonder whether one could reconfigured the line drivers "on-the-fly" an
drive the low speed mode from the FPGA fabric, bypassing the SERDES et
hardware blocks.

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[mickyc]

On Friday, 19 December 2014 10:23:47 UTC+1, mnentwig wrote:
I've heard the same, that the low-rate mode is one problem. Don't thin
you
can bring up the interface in HSx mode in a standardized way
(product-specific "hacks" via some 3-wire interface etc could stil
work).
I wonder whether one could reconfigured the line drivers "on-the-fly
and
drive the low speed mode from the FPGA fabric, bypassing the SERDES etc
hardware blocks.

---------------------------------------
Posted through http://www.FPGARelated.com

the low-speed can be patched in if desired.
for some reason I did think there are more complications ..

Does M-PHY "turn-off" transmission and expect a fast wake-up time? The FPG
transceivers and related PLLs would take a while to come up (and would nee
to be reset afaik). Googling M-PHY gives a lot of mentions o
sleep/hibernate but I can't find a good reference document...

I know DigRF3G (which is related to some extent I think) has requirement
like this (at much lower rates, it doesn't need FPGA SERDES just LVDS).


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[mnentwig]

my understanding is that the "PLL power-up & stabilization time" i
implementation dependent. The master continues in HS mode by sending SYN
symbols, then "start-of-frame". The SYNC does what its name promises, s
maybe there is no need to be fast.
That said, I wouldn't bet too much money on this superficial analysis. An
yes, the low speed mode is probably not the only problem...

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