minimum clock period of a combinational circuit

D

dila77

Guest
Hi,
please, how can I find out the minimum clock period (the maximum cloc
frequency in MHz) of a combinational circuit (for example, for a ful
adder) ?
After the synthesizing and implementation I got the following message:

Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 9.033ns

Is there any way to know the minimum clock period ?

Thanks :)



---------------------------------------
Posted through http://www.FPGARelated.com
 
Hi,
please, how can I find out the minimum clock period (the maximum clock
frequency in MHz) of a combinational circuit (for example, for a full
adder) ?
After the synthesizing and implementation I got the following message:

Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 9.033ns

Is there any way to know the minimum clock period ?

Thanks :)
Click to expand...
Is your adder driven by data that is clocked? Looking at the report i
seems that there are no clocked devices in your design. The minimum perio
will be derived using the worst case delay between clocked primitives. I
you dont have any it cant calculate it.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
On Nov 22, 2:19 pm, "dila77" <dila77@n_o_s_p_a_m.live.com> wrote:
Hi,
please, how can I find out the minimum clock period (the maximum clock
frequency in MHz) of a combinational circuit (for example, for a full
adder) ?
After the synthesizing and implementation I got the following message:

Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 9.033ns

Is there any way to know the minimum clock period ?

Thanks :)

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
You likely have no flip-flops in your design - i.e. you wrote
something like
begin
Y <= A + B;
end
clock frequency is driven by the maximum amount of time required to
get from one FF to another. What you probably want to do is put an FF
on your inputs (A and B), and your output (Y), all clocked by the same
clock signal.

Alternatively, the maximum data rate through your adder is the
reciprocal of the max combinatorial delay - but this essentially
assumes there are ideal FFs on the input and output and that setup and
hold times are met.

Welcome to the wonderful world of digital logic.

Chris
 
On Nov 23, 9:43 am, Chris Maryan <kmar...@gmail.com> wrote:
On Nov 22, 2:19 pm, "dila77" <dila77@n_o_s_p_a_m.live.com> wrote:



Hi,
please, how can I find out the minimum clock period (the maximum clock
frequency in MHz) of a combinational circuit (for example, for a full
adder) ?
After the synthesizing and implementation I got the following message:

Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 9.033ns

Is there any way to know the minimum clock period ?

Thanks :)

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

You likely have no flip-flops in your design - i.e. you wrote
something like
begin
  Y <= A + B;
end
clock frequency is driven by the maximum amount of time required to
get from one FF to another. What you probably want to do is put an FF
on your inputs (A and B), and your output (Y), all clocked by the same
clock signal.

Alternatively, the maximum data rate through your adder is the
reciprocal of the max combinatorial delay - but this essentially
assumes there are ideal FFs on the input and output and that setup and
hold times are met.

Welcome to the wonderful world of digital logic.

Chris
Click to expand...
But also note that the delay listed in the synthesis report is only
approximate, and if your design has nothing else in it, it represents
a pin to pin delay including the input and output buffers. The
actual delay through a combinatorial adder inside the chip will
be much less than the reported 9 ns.

-- Gabor
 
On Nov 23, 9:43=A0am, Chris Maryan <kmar...@gmail.com> wrote:
On Nov 22, 2:19=A0pm, "dila77" <dila77@n_o_s_p_a_m.live.com> wrote:



Hi,
please, how can I find out the minimum clock period (the maximu
clock
frequency in MHz) of a combinational circuit (for example, for a full
adder) ?
After the synthesizing and implementation I got the followin
message:

Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
=A0 =A0Minimum period: No path found
=A0 =A0Minimum input arrival time before clock: No path found
=A0 =A0Maximum output required time after clock: No path found
=A0 =A0Maximum combinational path delay: 9.033ns

Is there any way to know the minimum clock period ?

Thanks :)

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

You likely have no flip-flops in your design - i.e. you wrote
something like
begin
=A0 Y <=3D A + B;
end
clock frequency is driven by the maximum amount of time required to
get from one FF to another. What you probably want to do is put an FF
on your inputs (A and B), and your output (Y), all clocked by the same
clock signal.

Alternatively, the maximum data rate through your adder is the
reciprocal of the max combinatorial delay - but this essentially
assumes there are ideal FFs on the input and output and that setup and
hold times are met.

Welcome to the wonderful world of digital logic.

Chris

But also note that the delay listed in the synthesis report is only
approximate, and if your design has nothing else in it, it represents
a pin to pin delay including the input and output buffers. The
actual delay through a combinatorial adder inside the chip will
be much less than the reported 9 ns.

-- Gabor
Click to expand...


thanks a lot for your replies :)

actually I have an assignment (or you can say a small project). I have t
compare between many types of adders (Ripple carry adder, carry skip adder
carry lookahead adder, parallel prefix adder) in terms of delay and area.
So I'm confused how to do it, should I program it using the structural mod
in VHDL or should I use a clk signal to know the delay of each of them.
I'm a beginner in VHDL and I'm not sure how to do it?

Can anyone please tell me what's the best way to find out the delay of eac
adder??

Thanks a lot

---------------------------------------
Posted through http://www.FPGARelated.com
 
thanks a lot for your replies :)

actually I have an assignment (or you can say a small project). I have to
compare between many types of adders (Ripple carry adder, carry ski
adder,
carry lookahead adder, parallel prefix adder) in terms of delay and area.
So I'm confused how to do it, should I program it using the structura
mode
in VHDL or should I use a clk signal to know the delay of each of them.
I'm a beginner in VHDL and I'm not sure how to do it?

Can anyone please tell me what's the best way to find out the delay o
each
adder??

Thanks a lot
Click to expand...
I think that this is the wrong group to be posting to. Tr
comp.homework.freehelpwanted
;-)


---------------------------------------
Posted through http://www.FPGARelated.com
 
dila77 <dila77@n_o_s_p_a_m.live.com> wrote:

please, how can I find out the minimum clock period (the maximum clock
frequency in MHz) of a combinational circuit (for example, for a full
adder) ?

After the synthesizing and implementation I got the following message:
Click to expand...
Put a register before and after the block you want times,
and have the tools find the fastest clock for that system.

That works as a first approximation, but isn't perfect, as it could
includes much routing that you would not want in the timing,
especially if your device (even if you aren't loading into an
actual FPGA) might be way too big.

You could try with two latches on each side, such that two would
configure close to the actual logic, and two on the IOBs.
Verify that the two are actually close, such that the timing
is close.

The actual result will depend on how they are configure into a
real design. The above shouldn't be so far off, if you want
to build systolic array processors. You could do a series of
adders and registers for each test, maybe enough to fill up an
FPGA to about half full. (As it gets fuller, the routing will
be less optimal.)

-- glen
 
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