Mimcap

[Dmitriy Shurin]

I use Cadence v. 5.0.0 sub-version 5.0.33_USR2.34.8. The kit i
work with is tsmc 0.18u.
I am trying to build a mimcap without using ctmdummy layer.
While running drc I have no errors ,however while running extract
i receive an error "capv56 does not connect to two layers".
I think that divaext.rul does not recognize my layout as a mimcap.
Is there any way to build a mimcap without using ctmdummy layer?
I have to reduce the pitch...


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[Richard Griffith]

Dmitriy Shurin wrote:

I use Cadence v. 5.0.0 sub-version 5.0.33_USR2.34.8. The kit i
work with is tsmc 0.18u.
I am trying to build a mimcap without using ctmdummy layer.
While running drc I have no errors ,however while running extract
i receive an error "capv56 does not connect to two layers".
I think that divaext.rul does not recognize my layout as a mimcap.
Is there any way to build a mimcap without using ctmdummy layer?
I have to reduce the pitch...

Look at the extract deck. I expect the ctmdummy layer is required to
recognize the device.

I can't check the process manual but the cap would normally be made of
metal5, nitride, metal5a, capv56, metal6 (the nitride is probably not
drawn just part of the fabrication process). The capacitor is across the
nitride between metal5 and metal5a. Connections to the cap are made a
metal5 and metal6. The capv56 is used to connect metal5a to metal6. (I
could be wrong about the structure).

I have to reduce the pitch..

You do realize by doing this you are making the simulation model invalid.



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