MII SFD Detection with Shematics

Hello,
I have to detect the Start of a Ethernet Frame. So I want to make use of a FPGA. The FPGA will be connected to the MII pins of the PHY (TXD 0-3 and RXD 0-3, the Clocks, TX_EN and RX_DV). What I know from the IEEE802.3 Datasheets is that the preamble will be send as 14 Nibbles and after that 2 Nibbles the SFD.
In transmitting case it will be like that:
TxD0 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data
TxD1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data
TxD2 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data
TxD3 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Data
TxEn 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1..

So I thought that I can trigger the rising edge from TxD3 in the 16. Cylce or from Tx_En. But if I only check one wire there could be errors right? How do I check for more than one Cylce? Do I need a State machine?
Is this the correct path?

I found the example of SFD detection from OpenCores.org of the EtherMac project, but i dont have any verilog or vhdl knowledge.

Thatswhy i wanted to use the Xilinx ISE Schematic tool.
So can you help me by giving me some advice how to make use of some fast logic.
Do i need some FIFOs oder Latches?

Thank you very much and greetings

 

[glen herrmannsfeldt]

bln5320@googlemail.com wrote:

I have to detect the Start of a Ethernet Frame. So I want to
make use of a FPGA. The FPGA will be connected to the MII pins
of the PHY (TXD 0-3 and RXD 0-3, the Clocks, TX_EN and RX_DV).
What I know from the IEEE802.3 Datasheets is that the preamble
will be send as 14 Nibbles and after that 2 Nibbles the SFD.

In transmitting case it will be like that:
TxD0 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data
TxD1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data
TxD2 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data
TxD3 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Data
TxEn 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1..

You could crosspost to comp.dcom.lans.ethernet.

Though there isn't so much traffic over there, it still seems like
the right place.

-- glen

 

You could crosspost to comp.dcom.lans.ethernet.



Though there isn't so much traffic over there, it still seems like

the right place.



-- glen

Thanks for the advice I will also try my luck there.

So for the question with the Schematic in generell. How do I check for Signals that are High for more than one Cylce.
Something like:
If Tx_En is asserted
begin to check:
Signal ( TxD0 & TxD2) == 1 for 16 Cylces
Signal ( TxD1 ) == 0 for 16 Cycles
Signal ( TxD3 ) == 0 for 15 Cycles and after that its rising to 1
output SFD detected!

If its not possible with logic from schematics I have to learn some verilog and vhdl

Thanks and greetings

 

[Gabor]

bln5320@googlemail.com wrote:

You could crosspost to comp.dcom.lans.ethernet.



Though there isn't so much traffic over there, it still seems like

the right place.



-- glen

Thanks for the advice I will also try my luck there.

So for the question with the Schematic in generell. How do I check for Signals that are High for more than one Cylce.
Something like:
If Tx_En is asserted
begin to check:
Signal ( TxD0 & TxD2) == 1 for 16 Cylces
Signal ( TxD1 ) == 0 for 16 Cycles
Signal ( TxD3 ) == 0 for 15 Cycles and after that its rising to 1
output SFD detected!

If its not possible with logic from schematics I have to learn some verilog and vhdl

Thanks and greetings

You'd use the same structures whether it's schematics or HDL.
For each bit you need history of the most recent 16 cycles. This
usually means you want a 16-bit serial-in parallel-out shift-register.
Look for the desired bit patterns on the output of the S/R.
This generally means a 16-bit AND gate with various inputs inverted.
If this pattern could crop up unexpectedly during a data packet,
you'd need some additional logic to filter it out. For that,
a state machine may be better. There's nothing to say you can't
have a schematic based design with state machines, but most
people generally use HDL for that. When I was designing FPGA's
with schematics, all of my state machines were HDL "macros"
instantiated in the schematic.

-- Gabor

 

Ouch; state machines in schematics... that brings back some painful memories.

I usually used a ROM with feedback from Q to A. Some data bits were outputs. Some address bits were inputs.

I also occasionally used a state register that fed the control lines to a mux, whose outputs fed the state register. The inputs to the mux defined next state and any outputs.

HDL is SO much easier...

Andy

 

[HT-Lab]

On 13/12/2012 23:14, jonesandy@comcast.net wrote:

Ouch; state machines in schematics... that brings back some painful memories.

Interesting, I can't imagine designing state machines in anything else
but schematics ;-)

I use HDL Designer to quickly draw a bubble diagram and let the tool
generate whatever HDL I want (VHDL/Verilog/1,2,3 process statemachine,
sync/async reset, encoding style, etc.).

Hans
www.ht-lab.com

I usually used a ROM with feedback from Q to A. Some data bits were outputs. Some address bits were inputs.

I also occasionally used a state register that fed the control lines to a mux, whose outputs fed the state register. The inputs to the mux defined next state and any outputs.

HDL is SO much easier...

Andy

 

[glen herrmannsfeldt]

HT-Lab <hans64@htminuslab.com> wrote:

On 13/12/2012 23:14, jonesandy@comcast.net wrote:
Ouch; state machines in schematics... that brings back some painful memories.

Interesting, I can't imagine designing state machines in anything else
but schematics ;-)

There are state machine design tools, but the usual meaning of
schematic is you move gates and registers around, then connect
the inputs and outputs with lines. Be careful that the lines
aren't on top of previous ones, where they might accidentally
connect. (Some editors make such accidents easier than others.)

Fortunately I never did that before learning verilog. I did some for
other projects after using verilog, though. I find it much easier
to hand convert to verilog than to work on something in the
schematic editor.

I use HDL Designer to quickly draw a bubble diagram and let the tool
generate whatever HDL I want (VHDL/Verilog/1,2,3 process statemachine,
sync/async reset, encoding style, etc.).

-- glen

 

[Jon Elson]

HT-Lab wrote:

On 13/12/2012 23:14, jonesandy@comcast.net wrote:
Ouch; state machines in schematics... that brings back some painful
memories.

Interesting, I can't imagine designing state machines in anything else
but schematics ;-)
Huh? Real electrical schematics? Are you sure?
I use HDL Designer to quickly draw a bubble diagram and let the tool
generate whatever HDL I want (VHDL/Verilog/1,2,3 process statemachine,
sync/async reset, encoding style, etc.).

Oh, the state machine designer. Yes, that actually works, up to about
20 states. When you get up there, the page becomes VERY unwieldy,
and the self-documenting concept kind of falls apart. I tried it, ONCE,
and decided that:

if state = x1 then
if y=z then
state = x2

works a lot better.

Jon

 

Sorry, but bubble diagrams of state machines drawn in HDL Designer are not schematics!

I would like a tool that converts HDL into a re-arrangeable graphical bubble diagram (they never seem to arrange the diagram the way I intended it) for documentation.

HDL source is portable and maintainable long after HDL Designer is obsolete, license expired, etc. And the machine-generated HDL source code is rarely very human readable.

Andy