microblaze on XSV800

[Bhanu Nagendra P.]

I created an compiled a project to create bit file using the microblaze
EDK 3.2. I can successfully create the bit file combining both the HW/SW
streams and download it onto my XSV-800 board.
I have a couple of questions:

* However after I download the design onto the board, all output pins
continuously go high. Specifically I redirected the output on one of
one of the pushbuttons and even this pin is perpetually high. Does anybody seen
anything like this before.

* When I look up the ncd file generated on an fpga-editor, I notice that
the clock
distribution does not take place over the clock-distribution network on
the fpga, but instead on the long and short signal nets. Why is this the
case?

Any help is greatly appreciated.
Thanks,
-Bhanu

 

[Austin Lesea]

You may want to consider askign your question to the Xilinx University Newsgroup:

http://www.xilinx.com/univ/xup/course.htm#ug

Student/University questions are probably best handled by this forum (thanks to
MIT).

Austin

"Bhanu Nagendra P." wrote:

I created an compiled a project to create bit file using the microblaze
EDK 3.2. I can successfully create the bit file combining both the HW/SW
streams and download it onto my XSV-800 board.
I have a couple of questions:

* However after I download the design onto the board, all output pins
continuously go high. Specifically I redirected the output on one of
one of the pushbuttons and even this pin is perpetually high. Does anybody seen
anything like this before.

* When I look up the ncd file generated on an fpga-editor, I notice that
the clock
distribution does not take place over the clock-distribution network on
the fpga, but instead on the long and short signal nets. Why is this the
case?

Any help is greatly appreciated.
Thanks,
-Bhanu