Microblaze Cache

[alastair]

Hi,

I'm trying to enable the instruction cache on the Microblaze to
compare the speed of executing code from BRAM with SRAM plus cache.

I'm using the Insight XC2V1000 board with EDK 3.2. In a piece of test
code which executes from SRAM, I enable the cache using
microblaze_enable_icache() and disable using
microblaze_disable_icache(). Any code between the enable and disable
instructions does not get executed. I haven't checked that bit 26 of
the MSR is set yet, but that's the next thing to verify.

Has anyone else had a similar problem ? Should I try setting the MSR
bit in assembly ?

I use the default value for the tag address bits and the cache covers
the whole of the available SRAM. Below is the section of the MHS file
defining my Microblaze:

BEGIN microblaze
PARAMETER INSTANCE = mblaze
PARAMETER HW_VER = 2.00.a
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 1024
PARAMETER C_ICACHE_BASEADDR = 0xffe00000
PARAMETER C_ICACHE_HIGHADDR = 0xffefffff
BUS_INTERFACE DLMB = d_lmb
BUS_INTERFACE ILMB = i_lmb
BUS_INTERFACE DOPB = opb_bus
BUS_INTERFACE IOPB = opb_bus
END

Thanks,

Alastair.