P
prav
Guest
Hi all,
I am using Xilinx viretx 2 pro device (1152)package which has 8 MGT's.
for each of the MGT there are 9 dedicated pins which are TXP, TXN,
RXP, RXN,
AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, and GNDA.
In my design i am not using any of the MGT's.
The data sheet suggests that VTRX is the Input Receive termination
supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V).
Since i am not using the MGT's i wanted to know wether i should keep
these pins open OR tie it to 2.5 V.
Thanks in advance.
Rgds,
prav
I am using Xilinx viretx 2 pro device (1152)package which has 8 MGT's.
for each of the MGT there are 9 dedicated pins which are TXP, TXN,
RXP, RXN,
AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, and GNDA.
In my design i am not using any of the MGT's.
The data sheet suggests that VTRX is the Input Receive termination
supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V).
Since i am not using the MGT's i wanted to know wether i should keep
these pins open OR tie it to 2.5 V.
Thanks in advance.
Rgds,
prav