M
Madhulina Sinha
Guest
Suppose I have a processor which in first stage performs some addition
operation.Then the
results are latched in some registers.Then those latched results are
fed to another adder.During
simulation using test bench I can onlytest the final outputs from the
processorat different time unit.But I want to see the intermediate
latched results at different time unit.How can it be done
using verilog test bench.
operation.Then the
results are latched in some registers.Then those latched results are
fed to another adder.During
simulation using test bench I can onlytest the final outputs from the
processorat different time unit.But I want to see the intermediate
latched results at different time unit.How can it be done
using verilog test bench.