Metastability and Synchronization

[rsk]

hi friends,

I am very much confused with metastability and synchronisation
concepts.

One says we cant avoid this metastability,then how we are
dealing with this problem in ASIC design.

And one more thing how to synchronise two systems which are having
differnt phases.

I hope you guys will clarify me.

I want to know in detail on both of these topics so if you people have
any websitelinks or pdf files on these topics will you kindly forward
them to me(I hope you dont mind in doing this)

Many thanks to alex,sudhir,larry,mittrastephen williams and john for
responding and claifying my doubt on pesudo random number generator.



Have a very nice day dear friends

bye
ravi...

 

[Bob Perlman]

On Thu, 08 Apr 2004 00:34:07 -0400, "rsk" <krs_1980@yahoo.co.in>
wrote:

hi friends,

I am very much confused with metastability and synchronisation
concepts.

One says we cant avoid this metastability,then how we are
dealing with this problem in ASIC design.

You can't eliminate metastability, but with the proper design
techniques you can make the probability of system upset exceedingly
small.

And one more thing how to synchronise two systems which are having
differnt phases.

I hope you guys will clarify me.

I want to know in detail on both of these topics so if you people have
any websitelinks or pdf files on these topics will you kindly forward
them to me(I hope you dont mind in doing this)

Try:

http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm

The fpga-faq site also maintains an archive of comp.arch.fpga, which
you can search for even more information.

Bob Perlman
Cambrian Design Works

 

[Alexander Gnusin]

"rsk" <krs_1980@yahoo.co.in> wrote in message news:<7c0fcc456f034d70226478bb6007caac@localhost.talkaboutprogramming.com>...

hi friends,

I am very much confused with metastability and synchronisation
concepts.

One says we cant avoid this metastability,then how we are
dealing with this problem in ASIC design.

And one more thing how to synchronise two systems which are having
differnt phases.

I hope you guys will clarify me.

I would recommend to start from the following reading:

1. http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk_rev1_1.pdf
(There are also another papers on this site such as async FIFO design)

2.https://solvnet.synopsys.com/wwwauth/wwwauth:8000/news/pubs/snug/india2002/SNUG_multiple_clock_paper.PDF
(need to register as synopsys user)

3. http://www-ee.technion.ac.il/~ran/papers/Sync_Errors_Feb03.pdf

There is also goood parer presented by @HDL on the latest DVCON:
"Verifying Synchronization in Multi-Clock Domain SoC". You may get
from @HDL or EDACAFE sites (need to register).

Regards,
Alexander Gnusin

 

[glen herrmannsfeldt]

Bob Perlman wrote:

(snip)

You can't eliminate metastability, but with the proper design
techniques you can make the probability of system upset exceedingly
small.

With asynchronous (also called self-timed) logic, you can eliminate
system failure due to metastability, or so I am told. The system
will wait for the logic to settle, no matter how long it takes.

-- glen