Mess with repeat in non-blocking assignments

[Mike]

I have problem in understanding the way "repeat" works in a non-
blocking assignment as shown in the code (marked <<--- )

Point of interest in the code below starts

At T==35, valid == 1, @posedge clk
out is scheduled to have 88 after 4 clk cycles, which is T==75 (as per
<<----)

At T==45, valid == 0, @posedge clk
out == 11 at T==45 (as per line marked %% of verilog code)

At T==55, valid == 0, @posedge clk
out == 11 at T==55
;
;
At T==75, valid == 0, @posedge clk
out == ?? at T== 75.

At T==35, as per (<<---) lineof code, out is scheduled to be 88 at
T==75
and T==75, out is scheduled to be 11 because of line marked (%%) of
code.
Sim shows 88. I thought it should show 11, as it should have been
overwritten by 11 or atleast 'XX'.

At T==85, why is out still 88 ??? The only event scheduled at the
T==85 is 11 because of line marked %%, Why does it show still 88.

When "valid === 1'b0" and no more events present because of
line marked (<<----), "out" will be driven only by line marked (%%).

So out has to be "11", but "out" shows 88 ???

Any ideas,
Mike





module repeatScheduling ();

reg clk = 1'b0;

reg reset;
reg valid;

reg [7:0] value;
reg [7:0] out;

always
#5 clk <= ~clk;

initial
begin
reset <= #1 1'b1;
valid <= #1 1'b0;
repeat (1) @ (posedge clk);
reset <= #1 1'b0;
repeat (2) @ (posedge clk);
valid <= #1 1'b1;
repeat (1) @ (posedge clk);
valid <= #1 1'b0;
end

always @ (posedge clk)
begin
if (reset)
out <= 8'h0;
else
if (valid)
out <= repeat (4) @ (posedge clk) 8'h88; // <<------
else
out <= 8'h11; // %%
end


initial
begin
$dumpvars(0, repeatScheduling);
$dumpfile("repeatScheduling.vcd");
end

endmodule

 

Mike wrote:

At T==35, as per (<<---) lineof code, out is scheduled to be 88 at
T==75
and T==75, out is scheduled to be 11 because of line marked (%%) of
code.
Sim shows 88. I thought it should show 11, as it should have been
overwritten by 11 or atleast 'XX'.

At T==85, why is out still 88 ??? The only event scheduled at the
T==85 is 11 because of line marked %%, Why does it show still 88.

No, there are two events scheduled. One assigns 88 and the other
assigns 11. The final value will depend on which occurs last, and
that is considered nondeterministic in Verilog. This is a race
condition.

Nonblocking assignments do not perform any sort of descheduling of
previous schedules to a variable. Delayed assignments to Verilog nets
do what is called "inertial descheduling", keeping only the last
scheduled values. You can get "transport descheduling" with path
delays. But nonblocking assignments do not deschedule at all. All
scheduled assignments will occur.

There are some rules that were added to the LRM to get deterministic
ordering of nonblocking assignments in some situations. But this
situation is not one that they were intended to cover.