Merge parallel transistors on extract

[Raf Karakiewicz]

Hi,

I have a very large, cell-based circuit impossible to simulate. I would
like to see the behaviour of a small subset of these cells but would like
to include the non-linear, signal-dependant capacitive loading of the
other cells.

Assuming for now my cell consists of only one transistor, I would like to
tie the D,S,G of all transistors together. Now this doesn't help me in
simulation time as I still have the same number of transistors, UNLESS
extract could merge these transistors into ONE large transistor. I would
then only have the cells I want to simulate + 1 very large 'dummy' cell to
load my circuit. Can this be done?


Raf Karakiewicz
Electrical Engineer
rafal@eecg.toronto.edu

 

[David Enright]

Hi Raf,

I had a similar problem a few months ago. The simplest solution I found
was to use AWK on the extracted netlist.


David



Raf Karakiewicz <rafal@eecg.utoronto.ca> wrote in message news:<Pine.GSO.4.58.0406231350320.15083@ducks.eecg.toronto.edu>...

Hi,

I have a very large, cell-based circuit impossible to simulate. I would
like to see the behaviour of a small subset of these cells but would like
to include the non-linear, signal-dependant capacitive loading of the
other cells.

Assuming for now my cell consists of only one transistor, I would like to
tie the D,S,G of all transistors together. Now this doesn't help me in
simulation time as I still have the same number of transistors, UNLESS
extract could merge these transistors into ONE large transistor. I would
then only have the cells I want to simulate + 1 very large 'dummy' cell to
load my circuit. Can this be done?


Raf Karakiewicz
Electrical Engineer
rafal@eecg.toronto.edu

 

[Andrew Beckett]

AssuraRCX has a parameter "M Factor W" and "M Factor R" which reduces
parallel transistors. See the section on this in the Assura User Guide (in the
RCX chapter, in the Filtering Options section).

It's in Assura 3.1

Andrew.


On 2 Jul 2004 00:58:29 -0700, enright@ieee.org (David Enright) wrote:

Hi Raf,

I had a similar problem a few months ago. The simplest solution I found
was to use AWK on the extracted netlist.


David



Raf Karakiewicz <rafal@eecg.utoronto.ca> wrote in message news:<Pine.GSO.4.58.0406231350320.15083@ducks.eecg.toronto.edu>...
Hi,

I have a very large, cell-based circuit impossible to simulate. I would
like to see the behaviour of a small subset of these cells but would like
to include the non-linear, signal-dependant capacitive loading of the
other cells.

Assuming for now my cell consists of only one transistor, I would like to
tie the D,S,G of all transistors together. Now this doesn't help me in
simulation time as I still have the same number of transistors, UNLESS
extract could merge these transistors into ONE large transistor. I would
then only have the cells I want to simulate + 1 very large 'dummy' cell to
load my circuit. Can this be done?


Raf Karakiewicz
Electrical Engineer
rafal@eecg.toronto.edu

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd