Memory

[Kausi]

I need to implement a memory for my design. I have used-

reg [3:0] mem[0:3];

The snipet of my code is shown below-

always @(count)
begin
case(count)

3'b000 : begin Seg1<=7'b1000000; mem[0]=mem[0];mem[1]=mem[1];mem[2]
=mem[2];mem[3]=mem[3];end
3'b001 : begin Seg1<=7'b1111001; mem[0]=Code;mem[1]=mem[1];mem[2]
=mem[2];mem[3]=mem[3];end
3'b010 : begin Seg1<=7'b0100100; mem[0]=mem[0];mem[1]=Code;mem[2]
=mem[2];mem[3]=mem[3];end
3'b011 : begin Seg1<=7'b0110000; mem[0]=mem[0];mem[1]=mem[1];mem[2]
=Code;mem[3]=mem[3];end
3'b100 : begin Seg1<=7'b0011011; mem[0]=mem[0];mem[1]=mem[1];mem[2]
=mem[2];mem[3]=Code;end
default : begin Seg1<=7'b0101010; mem[0]=mem[0];mem[1]=mem[1];mem[2]
=mem[2];mem[3]=mem[3];end
endcase
end


assign Done= ((count==3'b100)|(!(count==3'b000)));

always @(posedge Done)
begin
if(Done) begin
if(((mem[0]==4'b1100)&(mem[1]==4'b1010)&(mem[2]==4'b0010)&(mem[3]
==4'b0111)))
Success=1'b1;
else Success=1'b0;
end
end
----------------------------------------------------------------------------------

The memory elements are forming a latch. Any workaround ?

Regards,
Kauser.

 

[Jonathan Bromley]

On Sun, 16 Nov 2008 05:15:39 -0800 (PST), Kausi
<kauser.johar@gmail.com> wrote:

I need to implement a memory for my design. I have used-

reg [3:0] mem[0:3];

The snipet of my code is shown below-
[...]
The memory elements are forming a latch. Any workaround ?

Not in any language in which "workaround" and "redesign"
have different meanings.

Having a clue about what your design is supposed to
do would be a good start. Avoiding meaningless
bits of code like
mem[0]=mem[0];
mem[1]=mem[1];
mem[2]=mem[2];
mem[3]=mem[3];
would also be good. Finally, ask yourself whether
you have any hope of making this work without a clock.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

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