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hariprem@gmail.com
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I have gone through modern approaches of verification specifically the
environments supported by VERA, System verilog. And i want to replicate
the same approach in verilog(conventional verifiaction).
As some directed memory timing checks are to be made i cannot totally
automate the testbench. Can anybody tell me about the preffered
approach to test memory model.
environments supported by VERA, System verilog. And i want to replicate
the same approach in verilog(conventional verifiaction).
As some directed memory timing checks are to be made i cannot totally
automate the testbench. Can anybody tell me about the preffered
approach to test memory model.