memory swapping

N

naran

Guest
I have a memory of 1024 location and data width is 16 bit.
i have modeled it using using with only the memory in the file.
Now i need to remove first 60 location and move the next 60 location
values to that position.
like this i have to move the subsequent values to the preceding 60
values untill i reach the last memory location.
Shall i have this part of memory module as external memory or i can
have it as an internal memory.
i am designing it for porting in FPGA.

Shall i use like the code below

module memory( );
---//input delcaration
-- //memory declaration
always @(posedge clk)
if(rst)
begin
end
else if(mem_rd==1)
begin end
else if(mem_wr==1)
begin end
else if ( swap_en==1)
begin
mem[off_wr]<=mem[off_rd];
mem[off_wr+1]<=mem[off_rd+1];
mem[off_wr+2]<=mem[off_rd+2];
----------------------
-----------------
mem[off_wr+59]<=mem[off_rd+59];
end
 
The code can be made somehow fully synthesizable but it will create
probably a very complex logic. Because it seems in the code that you
want to swap the 60-bytes in one clock cycle. The will cost 60 RAM
read-write decoder pairs, which is not a good design practice. You are
designing a 60-port Register File :)

Do you have to do it? If not, then you can swap it in 60 clock cycles,
but your logic will be extremely simpler than the one below. In each
clock cycle you will swap one word. Further, you can parameterize the
number of bytes to be swapped at the expense of clock latency.

If you have to do it in one clock cycle, then create "shadow" instance
of the RAM in the FPGA. But this will also cost additional logic which
"remembers" the swapped regions in the RAM.

Utku

I have a memory of 1024 location and data width is 16 bit.
i have modeled it using using with only the memory in the file.
Now i need to remove first 60 location and move the next 60 location
values to that position.
like this i have to move the subsequent values to the preceding 60
values untill i reach the last memory location.
Shall i have this part of memory module as external memory or i can
have it as an internal memory.
i am designing it for porting in FPGA.
Shall i use like the code below

module memory( );
---//input delcaration
-- //memory declaration
always @(posedge clk)
if(rst)
begin
end
else if(mem_rd==1)
begin end
else if(mem_wr==1)
begin end
else if ( swap_en==1)
begin
mem[off_wr]<=mem[off_rd];
mem[off_wr+1]<=mem[off_rd+1];
mem[off_wr+2]<=mem[off_rd+2];
----------------------
-----------------
mem[off_wr+59]<=mem[off_rd+59];
end
Click to expand...
 
Another point. Why do you have to swap? You can keep your 60 bytes in
the original location and the data which must be written there, can be
written somewhere else but you can put a "pointer" between the first
60 byte location and the second one. This is called "linked list".

Just an idea. It can make your design easier.

Utku.

On 3 Feb., 22:06, "Utku Özcan" <utku.oz...@gmail.com> wrote:
The code can be made somehow fully synthesizable but it will create
probably a very complex logic. Because it seems in the code that you
want to swap the 60-bytes in one clock cycle. The will cost 60 RAM
read-write decoder pairs, which is not a good design practice. You are
designing a 60-port Register File :)

Do you have to do it? If not, then you can swap it in 60 clock cycles,
but your logic will be extremely simpler than the one below. In each
clock cycle you will swap one word. Further, you can parameterize the
number of bytes to be swapped at the expense of clock latency.

If you have to do it in one clock cycle, then create "shadow" instance
of the RAM in the FPGA. But this will also cost additional logic which
"remembers" the swapped regions in the RAM.

Utku

I have a memory of 1024 location and data width is 16 bit.
i have modeled it using using with only the memory in the file.
Now i need to remove first 60 location and move the next 60 location
values to that position.
like this i have to move the subsequent values to the preceding 60
values untill i reach the last memory location.
Shall i have this part of memory module as external memory or i can
have it as an internal memory.
i am designing it for porting in FPGA.
Shall i use like the code below

module memory( );
---//input delcaration
-- //memory declaration
always @(posedge clk)
if(rst)
begin
end
else if(mem_rd==1)
begin end
else if(mem_wr==1)
begin end
else if ( swap_en==1)
begin
mem[off_wr]<=mem[off_rd];
mem[off_wr+1]<=mem[off_rd+1];
mem[off_wr+2]<=mem[off_rd+2];
----------------------
-----------------
mem[off_wr+59]<=mem[off_rd+59];
end
Click to expand...
 
On Feb 3, 4:28 pm, "Utku Özcan" <utku.oz...@gmail.com> wrote:
Another point. Why do you have to swap? You can keep your 60 bytes in
the original location and the data which must be written there, can be
written somewhere else but you can put a "pointer" between the first
60 byte location and the second one. This is called "linked list".
Click to expand...
Or if the goal was actually to shift the entire memory
up 60 locations, it could be done with a simple change
to the decode logic. Have an offset register that is added
to all addresses before decode. Adding 60 to that offset
register will then make it look like all the data has moved
by 60.

It is sort of like the difference between the "bubble-up"
implementation of a FIFO, and the circular read/write
pointer implementation.
 
sharp@cadence.com wrote:

Or if the goal was actually to shift the entire memory
up 60 locations, it could be done with a simple change
to the decode logic. Have an offset register that is added
to all addresses before decode. Adding 60 to that offset
register will then make it look like all the data has moved
by 60.
Click to expand...
Or even easier if you can afford to waste 4 bytes per 60, and use a
64-byte "window" each time. That way you just need to increment a
counter to use on the most significant address lines...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
Perhaps you can implement FIFO memory, maybe using two FIFOs?

Rethink your architecture - As you are moving the data to/from the
port, process it into memory along the way. Avoid having to come back
through reprocessing the same data.

(It sounds a little like you are processing an SDLC message from an
IMU.)

--troy
 
On Feb 5, 8:32 pm, "visiblepulse" <t...@visiblepulse.com> wrote:
Perhaps you can implement FIFO memory, maybe using two FIFOs?

Rethink your architecture - As you are moving the data to/from the
port, process it into memory along the way. Avoid having to come back
through reprocessing the same data.

(It sounds a little like you are processing an SDLC message from an
IMU.)

--troy
Click to expand...

Thanks Troy for u r reply.
I have modelled my memory as internal memory which needs to be
swapped.
And also by your suggestion do you mean to say that i need to use
twice the memory size of original for swapping operation.

---Naran
 
Not fully understanding your design requirements... But several times
I have needed to move memory, I write it into a second memory block
(or FIFO) as I am reading it from the first. Lastly, toggle a flag
indicating which memory block is now the current one. Memory is
swapped without even having to do anything. Bank it.
 
This technique is also called "ping-pong buffer", not FIFO.

But are the read and write clocks synchronous? Ping-pong buffers do
not suit asynchronous clock domain. FIFO is a superior architecture
for clock domain crossing.

On 9 Feb., 15:04, "visiblepulse" <t...@visiblepulse.com> wrote:
Not fully understanding your design requirements... But several times
I have needed to move memory, I write it into a second memory block
(or FIFO) as I am reading it from the first. Lastly, toggle a flag
indicating which memory block is now the current one. Memory is
swapped without even having to do anything. Bank it.
Click to expand...
 
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