Memory models in Icarus verilog

[[LinuxFc4]GaLaKtIkUs™]

I would like to model a memory bloc in Icarus Verilog so:
reg [7:0] mymem [0:1023];

But when I invoke the compiler (iverilog) I get a: I give up message.
After reading the docs I have seen that Icarus Verilog does't support
arrays of wire/regs.

Is there another way to medel a memory?

 

[[LinuxFc4]GaLaKtIkUs™]

OUPS.
reg [7:0] mymem [0:1023]; is not wrong ... what is wrong is array of
wires : wire [7:0] my aow[0:5];
And this is not a problem, It's possible to flatten the arrays (I think
that I'll very rarely face a situation with an array of wires of 1024
width !!).
Excuse me for perturbation !!