Memory Mapping

[Tarun]

Hello,
I'm working on a memory controller. I need to do memory mapping ie
logical to physical. I need to put up some kinda indexing . Should I
use a memory for this? and put the information in some kind of a RAM.
Please let me know what could be the best way to do this indexing.

 

[Jonathan Bromley]

On Wed, 03 Oct 2007 23:30:34 -0700, Tarun <reddbloke@gmail.com> wrote:

Hello,
I'm working on a memory controller. I need to do memory mapping ie
logical to physical. I need to put up some kinda indexing . Should I
use a memory for this? and put the information in some kind of a RAM.
Please let me know what could be the best way to do this indexing.

Are you familiar with how a translation lookaside buffer (TLB) works?
Think about it. If your logical address space is 32 bits, and your
memory pages are 4Kbytes (just examples, but quite reasonable ones)
then the logical address space is split into 1M pages. So you need
a 1Mx??? memory to store the whole page table. So, how do you
store just the small part of it that you're actually using? It's
essentially a cacheing problem. TLBs are the conventional way
to meet that need.

Yes, indeed you need some memory for the mapping. But it's
usual to store ALL the mapping information in conventional RAM,
where the operating system can get at it; then only the very
small part of the page table that's currently in active use
is stored in a hardware address translation unit - the TLB.
You can do useful work with a TLB of only a few dozen entries.
That's still probably big enough to warrant some kind of RAM
block rather than registers, but remember that it needs to be
*very* fast because, for *every* memory access, you must take
the hit of attempting to access the TLB (checking whether
your logical address is in there), extracting the page address
from it, and using that page address to construct the physical
memory address.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[glen herrmannsfeldt]

Jonathan Bromley wrote:

Are you familiar with how a translation lookaside buffer (TLB) works?
Think about it. If your logical address space is 32 bits, and your
memory pages are 4Kbytes (just examples, but quite reasonable ones)
then the logical address space is split into 1M pages. So you need
a 1Mx??? memory to store the whole page table. So, how do you
store just the small part of it that you're actually using? It's
essentially a cacheing problem. TLBs are the conventional way
to meet that need.

http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/BOOKS/dz9zr003/3.11.4

-- glen

 

Are you familiar with how a translation lookaside buffer (TLB) works?
Think about it. If your logical address space is 32 bits, and your
memory pages are 4Kbytes (just examples, but quite reasonable ones)
then the logical address space is split into 1M pages. So you need
a 1Mx??? memory to store the whole page table. So, how do you
store just the small part of it that you're actually using? It's
essentially a cacheing problem. TLBs are the conventional way
to meet that need.

http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/BOOKS/dz9zr003/3.11.4

That is an excellent example of an article which is formally correct
and utterly useless. The author appears incapable of clear
communication (or is determined to avoid it).

 

[glen herrmannsfeldt]

MikeShepherd564@btinternet.com wrote:

Are you familiar with how a translation lookaside buffer (TLB) works?
(snip)

http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/BOOKS/dz9zr003/3.11.4

That is an excellent example of an article which is formally correct
and utterly useless. The author appears incapable of clear
communication (or is determined to avoid it).

Did you continue on to the following pages? There is a whole subsection
on the TLB, but the link is only to the beginning of it.

In addition, that is part of the whole chapter on dynamic address
translation.

http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/BOOKS/dz9zr003/3.11

Though the purpose of this is to describe the specific implementation
used by IBM, not the general definition of the term.

-- glen