Memory initialization

[Steve]

Hello everyone,
I'm using a lookup table in my verilog design which i have to
initialize to non-zero values. The target FPGA is the outdated Xilinx
XC2S50. When i do the initialization in the code and synthesize the
code using Xilinx ISE, the code doesnot fit into the target FPGA. The
initialization looks like this:
inputs[0]=4'b1010;
inputs[1]=4'b1010;
inputs[2]=4'b1010;
inputs[3]=4'b1010;
inputs[4]=4'b1001;
inputs[5]=4'b1000;
inputs[6]=4'b0111;
..
..
..
..
..
..
inputs[62]=4'b1010;

is there any other way to initialize the memory locations? Why does it
utilize so much of hardware just to store values? Another strange thing
is that when all these locations are initialized to 4'b0000, then the
code fits into the target FPGA. Please help me with this problem.
Thank you.

 

[ngsayjoe@gmail.com]

Why don't you try to instantiate a ram library module instead? E.g.
spartan_ram_xxx

Joe,
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

Steve wrote:

Hello everyone,
I'm using a lookup table in my verilog design which i have to
initialize to non-zero values. The target FPGA is the outdated Xilinx
XC2S50. When i do the initialization in the code and synthesize the
code using Xilinx ISE, the code doesnot fit into the target FPGA. The
initialization looks like this:
inputs[0]=4'b1010;
inputs[1]=4'b1010;
inputs[2]=4'b1010;
inputs[3]=4'b1010;
inputs[4]=4'b1001;
inputs[5]=4'b1000;
inputs[6]=4'b0111;
.
.
.
.
.
.
inputs[62]=4'b1010;

is there any other way to initialize the memory locations? Why does it
utilize so much of hardware just to store values? Another strange thing
is that when all these locations are initialized to 4'b0000, then the
code fits into the target FPGA. Please help me with this problem.
Thank you.